Electric lamp and discharge devices: systems – Current and/or voltage regulation
Reexamination Certificate
2001-09-19
2002-05-21
Philogene, Haissa (Department: 2821)
Electric lamp and discharge devices: systems
Current and/or voltage regulation
C315S194000, C315S2090SC, C315S244000, C315S248000, C315SDIG004
Reexamination Certificate
active
06392366
ABSTRACT:
BACKGROUND OF INVENTION
The present invention is directed to an electrodeless fluorescent lamp circuit and more particularly to such a circuit which is also dimmable.
Phase-controlled dimmable ballasts have gained a growing popularity in industry due to their capability for use with photo cells, motion detectors and standard wall dimmers.
In incandescent lamp dimming systems, dimming is controlled by a phase dimmer, also known as a triac dimmer. A common type of phase dimmer blocks a portion of each positive or negative half cycle immediately after the zero crossing of the voltage. The clipped waveform carries both the power and dimming signal to the loads. The dimmer replaces a wall switch which is installed in series with a power line.
Dimming of fluorescent lamps can be accomplished by regulating the lamp current, or regulating the average current feeding the inverter. For electrodeless fluorescent lamps (EFLs), the pulse width modulating (PWM) technique has been used to provide a dimmable lamp. The PWM technique pulses the EFLs at full rated lamp current thereby modulating intensity by varying the percentage of time the lamp is operating at full-rated current. The technique is simple and is a fixed frequency operation, however, it requires control of the ballast inverter circuit by means internal to the ballast, adding to the cost and complexity of the ballast circuit. Another method utilizing frequency-shift keying (FSK) to lower power output from an r.f. inductor is disclosed in U.S. Pat. No. 6,175,198 issued to Louis R. Nerone (the present inventor). This method also requires control of the ballast inverter circuit by means internal to the ballast, adding to the cost and complexity of the ballast circuit. The above-described systems typically require at least one voltage bus having a filtered d.c. voltage, thereby requiring one or more electrolytic capacitors, adding to the cost and reducing the life expectancy of the ballast.
SUMMARY OF INVENTION
In an exemplary embodiment of the present invention, a ballast circuit for an electrodeless lamp designed to use a phase dimmer signal to control output of the electrodeless lamp is provided. The dimming ballast circuit includes a rectifier circuit for rectifying an input voltage from a phase dimmer source. The rectifier circuit includes rectifier diodes connected in a bridge rectifier arrangement having a pair of input nodes connected to the phase dimmer output for generating a pulsed d.c. voltage on a d.c. bus. A converter control circuit is coupled to the rectifier circuit for inducing an r.f. a.c. load current. The converter includes first and second complementary converter switches serially connected between the bus and a reference node. The switches are connected together at a common node through which the a.c. load current flows. Each switch also has a control node connected to a common control node, the voltage between the control node and the common node determining the conduction state of each of the switches. The converter also includes a first resistor connected between the d.c. bus and the control node and a second resistor connected between the reference node and the control node. A driving inductor is connected at one end to the common node and operatively connected at the remaining end to the control node. A load circuit is provided, including a resonant inductor connected at one end to the common node, with the resonant inductor mutually coupled to the driving inductor for sensing a voltage across the resonant inductor. An r.f. inductor is connected at one end to the remaining end of the resonant inductor for generating an r.f. field for powering the electrodeless lamp. A resonant capacitor is serially connected to the remaining end of the r.f. inductor. The resonant capacitor is connected at the remaining end to an intermediate node, wherein the resonant capacitor is a non-electrolytic capacitor. First and second d.c. blocking capacitors are connected between the bus node and the reference node and are joined at the intermediate node with the resonant capacitor. The blocking capacitors are non-electrolytic capacitors.
REFERENCES:
patent: 5796214 (1998-08-01), Nerone
patent: 5917289 (1999-06-01), Nerone et al.
patent: 5952790 (1999-09-01), Nerone et al.
patent: 6018220 (2000-01-01), Nerone
patent: 6051934 (2000-04-01), Nerone
patent: 6175198 (2001-01-01), Nerone
patent: 6218788 (2001-04-01), Chen et al.
Fay Sharpe Fagan Minnich & McKee LLP
General Electric Company
Philogene Haissa
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