Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1998-06-05
2002-04-09
Rose, Robert A. (Department: 2813)
Abrading
Abrading process
Glass or stone abrading
C451S029000
Reexamination Certificate
active
06368188
ABSTRACT:
RELATED APPLICATIONS
This application is related to the co-filed and commonly assigned application; attorney docket number AMDA.253PA, Ser. No. 09/092,533, entitled “A Method and Device for Analysis of Flip Chip Electrical Connections,” which is hereby incorporated by reference.
FIELD OF THE INVENTION
The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry associated with a flip chip bonded integrated circuit.
BACKGROUND OF THE INVENTION
The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Flip chip technology answers the demand for improved input/output (I/O) connections from the chip to external systems. On a flip chip, the electrical components are located (face down) on the side of the die which attaches to the chip package. In this manner, the flip chip provides a short interconnection length using, for example, ball-grid array (BGA) solder connections. The self-aligning nature of the solder bumps offers the advantages of higher density mounting, improved electrical performance and reliability, and better manufacturability. The positioning of the circuit side is the source of many advantages in the flip chip design. However, in other regards, the orientation of the die with the circuit side face down on a substrate is a disadvantage.
In one example, access to the circuit region is necessitated in order to modify or debug a finished chip. Additionally, access to the circuit region is often desired through manufacturing stages in order to test and analyze the circuit's integrity. In this event, it is necessary to cut through the body of the flip chip die or through the chip package in order to access the circuit region.
Various methods have been employed to access the circuit region. A popular method includes milling or grinding off portions of the die, or the chip packaging in order to access the circuit region. This method is not adequate, however, for all circuit testing purposes. The difficulty resides in the accuracy of this method as well as the wear the technique places on the circuit region. An example is provided with the need to study the quality of the electrical contacts in the circuit region or, conversely, to resolve the source of contact problems. A great deal of precision is needed to access specific regions of the contact. Fast milling simply is too rough a technique and may even add defects to the contact in the approach. When this happens it may be impossible to uncover the original flaw in the contact. Also, slow milling techniques are simply too inefficient for mass fabrication design testing and analysis.
For these reasons, it is necessary to uncover an alternative method and device for accessing the circuit region on a flip chip die. More specifically, an alternative method and device are needed to access and study the electrical contacts between the flip chip die and the chip package. The new method and device must avoid adding defects to the regions intended for analysis.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit technology and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A device and method are described which accord these benefits.
In particular, an illustrative embodiment of the present invention includes a method for accessing a circuit region on a flip chip die mounted on a chip package. The method includes removing a first portion of the flip chip die and the chip package. The flip chip die has a number of electrical connections to the chip package in the circuit region. A second portion of the flip chip die and the chip package is encapsulated. The second portion of the flip chip die and the chip package is attached to a tool. At least one of the number of electrical connections in the second portion is then accessed.
In another embodiment, a device for accessing a circuit region on a flip chip die mounted on a chip package is provided. The device includes a tool. An encapsulated portion of the flip chip die and the chip package is attached to the tool. The chip package has a number of electrical connections to the circuit region. The encapsulated portion of the flip chip die and the chip package includes an encapsulated exposed cross section of the circuit region.
In another embodiment, a system for accessing a circuit region on a flip chip die mounted on a chip package is provided. The system includes the device presented above as well as a controller. The controller is electrically coupled to the tool of the device in order to control its operation.
Thus an alternative method and device for accessing the circuit region on a flip chip die are provided. The new method and device provide increased accuracy for accessing the electrical contacts within the circuit region. Such a method and device is necessary in order to analyze and resolve flaws among the electrical contacts between a flip chip die and the chip package. The new method and device is precise enough to avoid adding defects upon approach to the contend intended for analysis. Specific regions of the electrical contact can be isolated for study. The technique is equally efficient for mass fabrication design testing and analysis.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4268946 (1981-05-01), Eisenberg
patent: 6106367 (2000-08-01), Dischiano
patent: 6139403 (2000-10-01), Dischiano
patent: 6144101 (2000-11-01), Akram
LandOfFree
Alternate method and device for analysis of flip chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Alternate method and device for analysis of flip chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alternate method and device for analysis of flip chip... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2864776