Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-04-29
2002-07-02
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169400
Reexamination Certificate
active
06414653
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a driving system for a plasma display panel (ACPDP) of a matrix display system.
Recently, as a display device becomes large in size, thickness of the display device is desired to be thin. Therefore, various types of display devices of thin thickness are provided. As one of the display devices, an ACPDP is known.
A conventional an ACPDP comprises a plurality of column electrodes and a plurality of row electrodes formed in pairs and disposed to intersect the column electrodes. A pair of row electrodes form one row (one scanning line) of an image. The column electrodes and the row electrodes are covered by dielectric layers respectively, at a discharge space. At the intersection of each of the column electrodes and each pair of row electrodes, a discharge cell (pixel) is formed.
FIG. 8
shows a timing chart of drive signals for driving the conventional ACPDP.
A reset pulse RPx of negative polarity is applied to each of the row electrodes X
1
-Xn. At the same time, a reset pulse RPy of positive polarity is applied to each of the row electrodes Y
1
-Yn. Thus, all of the row electrodes in pairs in the PDP are excited to discharge, thereby producing charged particles in the discharge space at the pixel. Thereafter, when the discharge is finished, wall charge is formed and accumulated on the discharge cell (A reset all at once period).
Here, in order to regulate the discharge and emission of light caused by the reset pulse which has no connection with the display and to improve the contrast, the reset pulses RPx and RPy having long rising time (long time constant) are used.
Then, pixel data pulses DP
1
-DPn corresponding to the pixel data for every row are applied to the column electrodes D
1
-Dm in order in accordance with display data. At that time, scanning pulses (selecting and erasing pulses) SP are applied to the row electrodes Y
1
-Yn in order in synchronism with the timings of the data pulse DP
1
-DPn.
At the time, only in the discharge cell (non-lighting pixel) to which the scanning pulse SP and the pixel data pulse DP are simultaneously applied, the discharge occurs, so that the wall charge produced at the reset all at once period is erased.
On the other hand, in the discharge cell to which only the scanning pulse SP is applied, the discharge does not occur. Thus, the wall charge produced at the reset all at once period is held. Namely, a predetermined amount of the wall charge is selectively erased in accordance with the pixel data (An address period).
Next, a discharge sustaining pulse IPx of negative polarity is applied to the row electrodes X
1
-Xn, and a discharge sustaining pulse IPy of negative polarity is applied to the row electrodes Y
1
-Yn at offset timing from the discharge row pulses IPx.
During the discharge sustaining pulses are continuously applied, the discharge cell which holds the wall charge sustains the discharge and emission of light (A discharge sustaining period). On the other hand, a discharge cell in which the wall charge is erased does not emit.
Then, wall charge erasing pulses EP are applied to the row electrodes Y
1
-Yn for erasing the wall charges formed in all discharge cells.
By repeating the cycle comprising the reset all at once period, address period, discharge sustaining period, and wall charge erasing period, the pixel display is performed.
As the PDP becomes large and fine, the wiring length of the row electrode is increased, and the width of the electrode is reduced. As a result, the wiring resistance of the electrode increases.
On the other hand, in the discharge sustaining period, a discharge current which flows in the discharge cell becomes maximum after several nanosecond from the start of the discharge sustaining pulse application, thereafter when several hundreds nanosecond elapses, the current stops. Since the interval between the discharge sustaining pulses is several microseconds, if, in selected respective discharge cells on a pair of row electrodes, discharges are approximately simultaneously started, a large discharge current flows instantaneously, which causes a large voltage down, thereby aggravating display characteristic.
In addition, the PDP has a narrow operating range for the driving voltage of the discharge. Therefore, if the DPD becomes large and fine, it is difficult to precisely control and manufacture the shape of the electrode and the thickness of the dielectric layer. Consequently, operating voltage and display characteristics vary at every panel.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a driving system for a plasma display panel which may improve display characteristics in accordance with respective panels, and may adjust each panel to a proper condition.
According to the present invention, there is provided a system for driving a plasma display panel having a plurality of row electrodes in pairs, a plurality of column electrodes intersecting with the row electrodes, first driving means for applying a row electrode driving pulse to each of the row electrodes, and second driving means for applying a pixel data pulse to each of the column electrodes, comprising, manual adjusting means for manually adjusting timing of rise edge and/or timing of fall edge of the row electrode driving pulse and/or the pixel data pulse.
The row electrode driving pulse includes reset pulses applied to the row electrodes in pairs for initializing all pixels, scanning pulses applied to one of the pair of row electrodes in order, discharge sustaining pulses applied to the row electrodes in pairs.
The manual adjusting means is provided for further adjusting a pulse width of the row electrode driving pulse and/or the pixel data pulse.
These and other objects and features of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.
REFERENCES:
patent: 5123039 (1992-06-01), Shoulders
patent: 5148461 (1992-09-01), Shoulders
patent: 5446344 (1995-08-01), Kanazawa
patent: 5724053 (1998-03-01), Nagakubo
patent: 5790087 (1998-08-01), Shigeta et al.
patent: 5818419 (1998-10-01), Tajima et al.
patent: 5854540 (1998-12-01), Matsumoto et al.
patent: 5917461 (1999-06-01), Sakami et al.
patent: 5963184 (1999-10-01), Tokunaga et al.
Arent Fox Kintner Plotkin & Kahn
Frenel Vanel
Pioneer Electronic Corporation
Shankar Vijay
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