Multiplex communications – Fault recovery – Bypass an inoperative switch or inoperative element of a...
Reexamination Certificate
2000-04-05
2002-07-09
Rao, Seema S. (Department: 2661)
Multiplex communications
Fault recovery
Bypass an inoperative switch or inoperative element of a...
C370S244000, C370S248000, C714S025000, C714S048000, C340S002100, C340S002800, C340S003430
Reexamination Certificate
active
06418116
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a transmission system having a switchover function for a plurality of transmission lines without producing momentary interruption of traffic.
BACKGROUND OF THE INVENTION
In conventional transmission systems, measures have been taken for switching transmission lines without producing momentary traffic interruption at the time of altering line configuration. In recent years, such uninterrupted switchover of lines has also been required even in the event of failure in equipment or a line for obtaining increased transmission quality especially in backbone transmission systems.
Generally, requirements for transmission lines can be classified into two: obtaining high quality and high reliability to carry traffics of emergency information, banking systems etc.; and obtaining large capacity with low cost for use in the Internet etc. where transmission quality is not regarded of great importance.
It is therefore required to cope with such variety of requirements for lines with the provision of better flexibility.
In
FIG. 5
, there is shown a block diagram to illustrate a conventional method for controlling an uninterrupted line switchover. In the example shown in
FIG. 5
, station (A)
10
and station (B)
20
are directly connected through a line
1
. Further, these stations are respectively connected through a line
2
to station (C)
3
which acts as transit equipment.
In the example shown in
FIG. 5
, line
1
is operated as an active line and line
2
is operated as a standby line. Both line
1
and line
2
transmit the identical data. Here, for station (A)
10
and station (B)
20
in
FIG. 5
, only related parts to the present invention i.e. a signal transmission portion in station (A)
10
and a signal reception portion in station (B)
20
are shown.
In
FIG. 6
, a time chart is shown illustrating the line switchover operation in the configuration shown in FIG.
5
. Signal timing corresponding to respective parts of a
1
, b
1
, c
1
, d
1
, e
1
and f
1
in
FIG. 5
is shown.
In
FIG. 5
, a frame pulse insertion circuit (FPINS)
11
in station (A)
10
is a circuit for inserting a frame pulse at the top of a frame to identify a switchover position. An output of frame pulse insertion circuit
11
is forwarded to a distribution circuit (DIS)
12
.
The output of frame pulse insertion circuit
11
is branched into two by distribution circuit
12
, to be forwarded respectively to active line
1
and standby line
2
. On the other hand, in a signal reception portion of station (B)
20
, there are provided a line selection circuit (SEL)
21
for selecting a line; alarm detection circuits (ALMDET)
22
and
23
for detecting line alarm conditions or received signal errors; and frame pulse detection circuits (FPDET)
24
and
25
for detecting a frame pulse to identify a switchover position in received signals.
Furthermore, a control circuit
26
controls an elastic memory
27
according to inputs from alarm detection circuits
22
and
23
and from frame pulse detection circuits
24
and
25
. Elastic memory
27
functions as a variable delay circuit which can variably adjust the amount of delay. On the other hand, a fixed-amount delay circuit
28
produces a fixed amount of delay against signals received through active line
1
.
Thus, control circuit
26
adjusts the amount of delay in elastic memory
27
so that the timing between a signal received from active line
1
and an identical signal received from standby line
2
may coincide. Thereafter each of these signals is input into line selection circuit (SEL)
21
.
Referring to
FIG. 6
, it is assumed that signal b
1
is transmitted on active line
1
and also signal a
1
is transmitted on standby line to station (C)
3
. There is a delay against signal a
1
produced in signal c
1
to be input into station (B)
20
via standby line
2
. (Refer to signal c
1
in
FIG. 6.
)
Control circuit
26
adjusts the amount of delay in elastic memory
27
using outputs of frame pulse detection circuits
24
and
25
, to adjust phases of the two signals (d
1
, e
1
in FIG.
6
).
Now, when a failure occurs in frame timings
1
and
2
in signal b
1
of active line
1
, the failure is detected by alarm detection circuit
23
. Signal b
1
receiving the failure is delayed in fixed-amount delay circuit
28
and is forwarded to line selection circuit
21
at the timing of signal e
1
.
Control circuit
26
then adjusts the amount of delay in elastic memory
27
to synchronize the timing of signal e
1
with the timing of signal c
1
input from the standby line, to forward to line selection circuit
21
as signal d
1
.
Line selection circuit
21
selects signal d
1
received through standby line
2
to substitute for signal e
1
on active line
1
under the control of control circuit
26
, to output signal f
1
. Thus effect of the failure to signal transmission is eliminated.
In the above conventional method, signal transmission is interrupted when alarm or error conditions simultaneously occur on both active line
1
and standby line
2
. To avoid this problem and keep signal traffic from interruption even in such cases, a method that a standby line is selected from a plurality of lines is applicable, using a method similar to the above.
However, in order to realize this method in a conventional way, delay circuits such as elastic memories must be implemented independently line by line. This requires increased amount of memories as well as complicated control circuits, making equipment large in scale.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a transmission system with a method for controlling uninterruptible line switchover for a plurality of lines to obtain high transmission quality even when using low quality lines and avoid unnecessary occurrence of line switchover, with minimal hardware configuration of memories, control circuit, etc.
It is another object of the invention to provide a transmission system with a method for controlling uninterruptible switchover for a plurality of lines having redundant configuration to keep or restore signal transmission from interruption and errors.
The following means is provided to solve aforementioned problems: A plurality of standby lines are provided for selecting to switch over, while conventionally there have been provided totally two lines each constituting an active line and a standby line. Also, a single elastic memory is provided for a plurality of lines to be selected in advance by a selection circuit, while a plurality of elastic memories have conventionally been provided corresponding to respective lines.
General method is described hereinafter prior to the explanation on the present invention. Signals are transmitted using a partition called ‘frame’. The normality of received signals is verified on frame basis i.e. frame by frame on the receiving side, and a switchover is carried out when necessary at the unit of frame after frame phases are synchronized for each line. Based on this method, if an error occurs on a line, signal transmission can be realized without an error at the output by replacing a frame having the error with a corresponding frame received on another line.
On the transmitting side, a top of a frame for phase synchronization is inserted and is branched to a plurality of lines to transmit. On the receiving side, an existence of alarm or error condition is examined at every frame of respective lines. After the phases are synchronized, line switchover is carried out at the unit of a frame when necessary.
The first feature of a transmission system according to the present invention having a control function of uninterruptible switchover of a plurality of lines is described below:
On the transmitting side there is provided a transmission portion which includes: a frame pulse insertion circuit for inserting a pulse at the top of each frame of a signal for phase synchronization; and a distribution circuit for branching the signal having the frame pulse to a plurality of lines.
On the receiving side, there
Fujitsu Limited
Rao Seema S.
Rosenman & Colin LLP
Sam Phirin
LandOfFree
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