Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-03-14
2002-03-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S132000, C438S215000, C438S281000, C438S467000, C438S601000
Reexamination Certificate
active
06359325
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the fabrication of microscale structures, such as metallization for microelectronic applications. More particularly, this invention relates to a method of forming nano-scale structures by initiating lateral grain growth from polycrystalline materials.
2. Description of the Prior Art
As represented in
FIG. 1
, backend of the line (BEOL) interconnect metallization
10
often includes an electrically-conductive layer
12
of an aluminum-copper alloy that is sandwiched between a pair of diffusion barrier layers
14
. The diffusion barrier layers
14
reduce the solid state diffusion rate between the conductive layer
12
and metals from surrounding metal structures, so as to improve the reliability and sheet resistance of the metallization
10
. In the past, metallization
10
of this type has been patterned by conventional lithographic techniques to produce various structural features, such as metal pads and lines. While lithographic techniques are widely and successfully used in the art, nano-scale features (i.e., operative structures and components that require a controlled dimension of less than ten nanometers) are difficult to form by conventional lithography. In view of the demand for greater miniaturization of microcircuits and their components, it would be desirable if a method were available that enabled the patterning of metallization to form nano-scale features.
SUMMARY OF THE INVENTION
The present invention provides a method of forming nano-scale features with conventional polycrystalline structures, such as metallization for microelectronic applications. A key aspect of the invention is the determination of the mechanism by which lateral grain growth can be induced and controlled in a multilayer structure having a polycrystalline layer and a second layer that serves as a constraining layer when the multilayer structure is heated. This mechanism is believed to involve the growth of grains that have been sectioned by patterning to have fewer than six grain boundaries, six grain boundaries being the most thermodynamically stable grain structure. If sufficiently heated, those grains having fewer than six boundaries and located at the patterned edge of the polycrystalline layer will undergo grain growth. If constrained, as is the case when the polycrystalline layer contacts a second layer with a lower coefficient of thermal expansion, stresses induced by the second layer will cause this grain growth to be predominantly lateral (i.e., two-dimensional and in the plane of the polycrystalline layer) and outward from the patterned edge of the polycrystalline layer.
In view of the above, the method of this invention generally entails forming a multilayer structure that includes a polycrystalline layer and at least one constraining layer. The multilayer structure is patterned to form first and second structures, each of which includes the polycrystalline and constraining layers. At least the first structure is then locally heated, during which time the constraining layer restricts the thermal expansion of the polycrystalline layer of the first structure. As a result, stresses are induced in the polycrystalline layer of the first structure, causing substantially two-dimensional grain growth from the edge of the first structure. Sufficient grain growth occurs to produce a third structure which is, based on an average grain size of, for example, 4 &mgr;m or less, a nano-scale structure, defined herein as designating a structure with at least one dimension that is less than ten nanometers. When appropriately configured, nano-scale structures formed in accordance with this invention can be an operative component of an electrical, mechanical, optical or fluid-handling device.
In view of the above a significant advantage of this invention is that nano-scale features can be selectively formed for devices that may be employed in a wide variety of applications. An important example is the forming of nano-scale features from conventional circuit metallization such as that shown in
FIG. 1
, in which the electrically-conductive layer
12
is a polycrystalline layer sandwiched between a pair of diffusion barrier layers
14
that serve as constraining layers. Notably, this invention makes use of a phenomenon that might otherwise be viewed as a flaw, as would be the case if the nano-scale feature creates an electrical short between adjacent interconnect metallizations.
Other objects and advantages of this invention will be better appreciated from the following detailed description.
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Clevenger Lawrence A.
Naeem Munir D.
August Casey P.
Hartman Domenica N. S.
Hartman Gary M.
Ho Tu-Tu
International Business Machines - Corporation
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