Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2000-09-28
2002-05-14
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S635000, C257S637000, C257S701000, C257S723000, C257S737000, C257S782000, C257S792000
Reexamination Certificate
active
06388337
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to methods for fabricating semiconductor devices, and more particularly, to a technique for post-processing a completed semiconductor wafer or device.
BACKGROUND OF THE INVENTION
Integrated circuit device chips are typically fabricated from semiconductor substrates upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. These electrical circuit elements are connected to one another through patterned conductor layers which are separated by insulator layers. These patterned conductor layers are referred to as metal layers or levels.
Conventionally, once the interconnecting metal layers are formed, a last metal layer is defined comprising bond pads or connection pads for access to the lower metal layers and the integrated circuitry of the device, which may comprise a plurality of discrete integrated circuit die or chips to be diced from the wafer. A final passivation layer is then applied over the entire surface and selectively etched to expose the bond pads to allow electrical connection to the integrated circuitry of the completed device via the metal levels.
SUMMARY OF THE INVENTION
Advantageously, applicants have recognized and disclose herein the desirability of performing further processing above the final passivation layer of the completed semiconductor device. For example, as one application, it may be desirable to form devices, such as charge-coupled devices (hereinafter also referred to as “CCDs”) above the final passivation layer, thereby integrating the CCDs with the semiconductor device or wafer. However, fabrication of such an integrated structure exposes the final passivation layer and more importantly, the uncovered bond pads of the semiconductor device to the chemicals and processes needed to form the post-process structures. For example, during color patterning of a CCD device being formed above the final passivation layer, the color patterning process used to develop out the photoresist could result in base/acid attack of the exposed bond pads.
The present invention is directed to facilitating post-processing above the upper surface of a conventionally fabricated and otherwise completed semiconductor device.
Briefly summarized, the invention comprises in one aspect a method for processing a semiconductor device. The method includes: providing the semiconductor device with at least one metal level, a final passivation layer protecting the at least one metal level, and bond pads exposed through the final passivation layer for accessing the semiconductor device via the at least one metal level; forming a protective film over the final passivation layer and the exposed bond pads of the semiconductor device, thereby providing a semiconductor device assembly; after forming the protective film, performing post-processing of the semiconductor device assembly; and subsequent to the post-processing, selectively etching the protective film to expose the bond pads.
In another aspect, the invention comprises a semiconductor device assembly which includes a conventional completed semiconductor device with at least one metal level, a final passivation layer protecting the at least one metal level and bond pads exposed through the final passivation layer for accessing the semiconductor device via the at least one metal level. The assembly includes a protective film over the final passivation layer, the protective film having openings aligned with the exposed bond pads of the semiconductor device to allow access thereto. A post-process structure is disposed above the protective film, having been formed above the protective film subsequent to completion of formation of the conventional semiconductor device with the at least one metal level, final passivation layer and exposed bond pads.
To restate, applicants disclose herein the desirability of performing “post-processing” above the final passivation layer of a completed semiconductor device or wafer, e.g., to integrate one or more additional structures with the semiconductor device. To accomplish this, a protective film is formed over the final passivation layer and exposed bond pads of the semiconductor device. This protective film delivers bond pad protection post final passivation formation and etching. The process disclosed herein is compatible with further semiconductor processing, and no special tools or process steps are required to implement the technique. Once in place, the protective film protects the otherwise exposed bond pads from moisture and metallic migration, such as ionics. Disclosed herein is a low-cost, fast throughput film deposition process for the formation of the protective film. The wafer temperature for formation of the film is compatible with back end of line thermal processing/budgeting. A robust process window for film deposition is available with negligible surface charging effects. For example, the protective film can be formed at a few Torr and 1.0 Kw of power.
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Michael James George
Miller Jeffrey Scott
Pittman Gary Dale
Previti-Kelly Rosemary Ann
Heslin Rothenberg Farley & & Mesiti P.C.
Nguyen Ha Tran
Radigan, Esq. Kevin P.
Walter, Jr. Esq. Howard J.
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