Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

1999-04-20

2002-01-01

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S762000, C257S767000

Reexamination Certificate

active

06335570

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof and, more particularly to a semiconductor device having a conductive layer including copper and a manufacturing method thereof.
2. Description of the Background Art
With recent increase in demand for higher integration degree and speed of the semiconductor device, various considerations are given to the material of a conductive layer. If a width of the conductive layer becomes smaller than about 0.15 &mgr;m, the selection of materials which can be used for the conductive layer would extremely be limited. Recently, the use of copper for the conductive layer has been described for example in “Damascene Cu interconnection capped by TiWN layer”
TECHNICAL REPORT OF IEICE, SDM
96-169 (1996-12).
FIG. 29
is a cross sectional view showing a structure of the conductive layer which is described in the aforementioned article. Referring to
FIG. 29
, a trench
92
is formed in an insulating layer
91
including silicon dioxide and formed on a silicon substrate. A conductive layer
94
including copper is formed in trench
92
with a barrier layer
93
including titanium nitride, tantalum or tantalum nitride in the interposed. A cap layer
96
including titanium tungsten nitride (TiWN) is formed to cover an upper surface of conductive layer
94
. Barrier layer
93
and cap layer
96
effectively prevent oxidation of conductive layer
94
and diffusion of copper in conductive layer
94
into insulating layer
91
, so that degradation of characteristic such as increase in electrical resistance of conductive layer
94
is effectively prevented.
Conventionally, a so-called dual damascene structure as shown in
FIG. 29
in which a multiple of conductive layers including copper are formed is described, for example, in 1997
Symposium on VLSI Technology Digest of Technical Papers
pp. 59-60.
FIGS. 30
to
38
are cross sectional views showing a method of manufacturing the dual damascene structure described in the above mentioned document. Referring to
FIG. 30
, an insulating layer
101
including silicon dioxide is formed on a silicon substrate, and a trench
102
is formed in insulating layer
101
. A first layer including titanium nitride, tantalum or tantalum nitride is formed to cover a surface of trench
102
, and a copper layer is formed on the first layer to fill trench
102
. The copper and first layers are planarized by CMP (Chemical Mechanical Polishing), so that a barrier layer
103
including titanium nitride, tantalum or tantalum nitride and a conductive layer
104
including copper are formed.
Formed on insulating layer
101
are a barrier layer
105
including silicon nitride, an insulating layer
106
including silicon dioxide, a barrier layer
107
including silicon nitride, an insulating layer
108
including silicon dioxide and a barrier layer
109
including titanium nitride, tantalum or tantalum nitride. By sequentially etching these layers, holes
111
and
110
are formed.
As shown in
FIG. 31
, when the etching is finished, a particle
112
of carbon fluoride (CF
x
), a particle
113
of cupric oxide (CuO), a particle
116
of copper fluoride (CuF
x
) or the like adhere to a sidewall of hole
110
. A cupric oxide layer
114
is formed on a surface of conductive layer
104
, and a cuprous oxide (Cu
2
O) layer
115
is formed therebelow. It is noted that barrier layers
103
,
105
,
107
and
109
as well as insulating layer
108
are not shown in
FIGS. 31
to
34
.
Referring to
FIG. 32
, oxygen plasma allows particles
112
and
116
of carbon and copper fluoride to be oxidized and disappeared.
Referring to
FIG. 33
, an oxide is reduced by hydrofluoric acid (HF). Thus, particle
113
of cupric oxide disappears and, cupric oxide layer
114
in conductive layer
104
is also reduced to form cuprous oxide layer
115
.
Referring to
FIG. 34
, cuprous oxide layer
115
is reduced by gaseous hydrogen to copper.
Referring to
FIG. 35
, a barrier layer
121
including titanium nitride, tantalum or tantalum nitride is formed to cover side surfaces of holes
110
and
111
and the surface of conductive layer
104
.
Referring to
FIG. 36
, an entire surface of barrier layer
121
is etched back to expose the surface of conductive layer
104
.
Referring to
FIG. 37
, a copper layer
123
is formed by CVD (Chemical Vapor Deposition).
Referring to
FIG. 38
, an entire surface of the copper layer is etched back by CMP to form a conductive layer
124
including copper. Thus, a dual damascene structure in which conductive layers
104
and
124
are connected is completed.
In the above described method, however, a step of cleaning hole
110
as shown in conjunction with
FIGS. 32
to
34
is required after holes
110
and
111
are formed, whereby the number of steps for manufacturing the semiconductor device disadvantageously increases.
Further, if hole
110
is formed with a diameter larger than a width of trench
102
in the step shown in
FIG. 30
such that a width of conductive layer
124
filling hole
110
is increased, a surface of insulating layer
101
is exposed by hole
110
. If hole
110
is filled with copper layer
123
, the copper is oxidized as it is in contact with silicon dioxide, so that electrical resistance of conductive layer
124
increases. In addition, as copper is diffused into insulating layer
101
, insulating characteristic of insulating layer
101
is impaired.
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned problem. An object of the present invention is to provide a semiconductor device having a conductive layer capable of effectively preventing diffusion of particles of copper or the like which form the conductive layer without any increase in the number of manufacturing steps.
Another object of the present invention is to provide a semiconductor device in which particles of copper or the like forming a conductive layer are not diffused to an insulating layer even when a width of the conductive layer is increased.
A semiconductor device according to the present invention includes a first insulating layer, first diffusion preventing layer, first conductive layer, second diffusion preventing layer, second insulating layer, third diffusion preventing layer and second conductive layer.
The first insulating layer is formed on a semiconductor substrate and has a recess. The first diffusion preventing layer is formed on a surface of the recess. The first conductive layer is formed on a surface of the first diffusion preventing layer to fill the recess. The second diffusion preventing layer is formed on a surface of the first insulating layer and provided with an opening which exposes a surface of the first conductive layer. The second insulating layer is formed on a surface of the second diffusion preventing layer to expose the surface of the first conductive layer and a part of the surface of the second diffusion preventing layer, and has a first hole communicating with the opening. The third diffusion preventing layer is formed on a side surface of the first hole and on the second insulating layer in contact with an upper surface of the second diffusion preventing layer. The second conductive layer fills the opening and the first hole such that it is in contact with the first conductive layer.
In the semiconductor device having the above described structure, a side surface of the opening is formed by the part of the surface of the second diffusion preventing layer, the side surface of the first hole is formed by the third diffusion preventing layer, and the third diffusion preventing layer is in contact with the upper surface of the second diffusion preventing layer. Thus, the portion of the second conductive layer which fills the opening and the first hole is in contact with the second and third diffusion preventing layers, so that the second conductive layer would not be in contact with the insulating layer even if a diameter of the first hole and a width of the first conductive

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