Radiation imagery chemistry: process – composition – or product th – Registration or layout process other than color proofing
Reexamination Certificate
2000-01-11
2002-01-22
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Registration or layout process other than color proofing
C430S030000
Reexamination Certificate
active
06340547
ABSTRACT:
TECHNICAL FIELD
The present invention broadly relates to semiconductor manufacturing processes involving photolithography techniques, and deals more particularly with a method for imaging circuit patterns on successively deposited layers of materials using two different image steppers having non-aligned optical systems.
BACKGROUND OF THE INVENTION
The art of photolithography commonly used in semiconductor manufacturing processes is well developed. With the trend towards increasing circuit density, there is a need for higher resolution and greater accuracy of alignment of the circuit patterns that are successively formed in overlying relationship on multiple layers deposited on a wafer. Circuit patterns are commonly imaged onto the wafer by so-called step-and-repeat machines or “steppers” which comprise a projection exposure system that transfers a reticle pattern containing the desired circuit onto a wafer substrate at a predetermined magnification through an optical projection system. These steppers include an optical alignment system, usually unique to each stepper manufacturer, which employs a series of alignment marks that are etched onto the wafer substrate such that successively imaged patterns on multiple layers built up on the substrate are optically aligned so as to be precisely registered with each other. Alignment accuracy is considered to be how accurately the patterns of one level match their corresponding patterns on other levels. For contact etching, photo resist patterning or wafer deposition, there are several alignment marks per wafer. If one of the layers is misaligned, then a serious defect will arise in the competed semiconductor device. The accuracy of the alignment process is also a major factor that determines the yield of completed devices. To achieve the necessary alignment precision, alignment marks are used that are incorporated into the chip and/or put in or on the edge of the wafer. Alignment marks are typically formed by etching a depth into the wafer. The etching causes a pattern with a step height in the wafer that acts as the alignment mark. One of the typical alignment marks is formed at the scribe lines of the wafer. As is well known in the art, a wafer provided with alignment marks formed therein is coated with a transparent photosensitive material, such as photo resist. The wafer is then loaded into the stepper. The stepper uses a laser beam with a fixed wavelength to sense the position of the alignment marks on the wafer by using the alignment marks as a reference point. The alignment marks are employed to adjust position of the wafer to precisely align it with the previous layer on the wafer. The interference from the alignment marks is reflected back to detecting devices in the stepper. The interference is also used as a signal to measure the exact position of the alignment marks.
As previously mentioned, the alignment mark pattern is typically formed in the alignment area or scribe lines of the wafer. Subsequent layers used to form the integrated circuit are formed over the wafer, thereby coving the original alignment mark pattern. The alignment mark is therefore replicated in the subsequently formed layers. As more layers are added to the integrated circuit, the alignment mark pattern is propagated upward with subsequent layers. In some fabrication processes, a polishing process is needed to remove a portion of the inter-level dielectric layer for achieving better topography.
One of the problems associated with building up the alignment mark pattern is that it is incompatible with certain manufacturing processes, such as a planarization process, where the surface of the wafer is planarized for a subsequently formed layer, by laying down a metal layer that provides a flat surface. With a metal layer deposited over the alignment mark pattern of the underlying layer, it may be appreciated that the replicated alignment mark in the inter level dielectric layer is removed during the polishing process. If a metal layer of polysilicon layer is then formed over the dielectric layer, the replicated alignment mark in these layers becomes invisible because the metal layer is opaque to the laser beam. Accordingly, it is impossible to then align the metal pattern to the contact pattern.
One solution to the above described problem of aligning alignment marks where the upper alignment mark is made invisible due to an overlying layer of material, involves the use of so-called “clear-out windows”. Clear-out windows are formed by plasma etching the top metal layer, until the underlying alignment mark on a lower material layer has been revealed. This lower alignment mark is then used by the stepper to align subsequently imaged patterns onto the top (metal) layer for further processing. However, the process of forming clear-out windows is relatively complicated and requires a substantial amount of time for fabrication.
As previously mentioned, the exact geometries and arrangement of alignment components in steppers are normally unique to each stepper manufacturer. This means that the alignment systems used by various stepper manufacturers are different, and thus are incompatible with each other. In other words, steppers from multiple manufacturers normally cannot be employed to form layers of circuit patterns on the same wafer for the reason that the layered circuit patterns would not be aligned since the alignment marks replicated by different steppers would not register with each other. In many operations this is not a problem because only a single stepper is employed to image the patterns on all layers of a given wafer. However there are some circumstances in which it would be desirable, if possible, to employ at least two different steppers to perform imaging operations on the same wafer. For example, a semiconductor foundry might be requested by a customer to form several preliminary material layers on a wafer before the wafer is shipped to the customer who later employs a second, differing stepper to image patterns on subsequently deposited layers of the wafers. In the event that the semiconductor foundry's stepper possess an alignment system different than that used by the customer, the ICs cannot be properly completed by the customer since the patterned layers will not be aligned with each other.
It would therefore be highly desirable to provide a method for forming circuit patterns on a semiconductor wafer using at least two imaging steppers respectively having different, non-aligned, optical alignment systems. The present invention is directed toward satisfying this need.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method is provided for forming circuit patters on a semiconductor wafer using first and second optical image steppers respectively having first and second differing optical alignment systems. The method includes the steps of: imaging a first alignment mark on a wafer using the first stepper; determining the two dimensional optical coordinate differences between the first and second alignment systems; translating the optical coordinates of the second alignment system based on the coordinate differences previously determined, whereby to correlate the second alignment system with the first alignment system and, imaging a second alignment mark on the wafer using the second alignment system and the translated optical coordinates, such that the first and second alignment marks are aligned in a common optical alignment system. Preferably, first and second blocks of pattern-free space are reserved on the wafer and a first alignment mark is performed by imaging the mark in the first block of space, and the second alignment mark is imaged in the second block of space. The method also desirably includes producing an overlay reference pattern exhibiting a set of desired alignment properties related to the alignment of the first and second alignment systems, and comparing the circuit patters on the wafer to the reference pattern in order to verify that the desired alignment between the first and second steppers has b
Chen Chia-Hsiang
Chen Ming-Fa
Hung Chih-Chien
Wong Fu-Tien
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
Young Christopher G.
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