Semiconductor memory device capable of adjusting internal...

Details Semiconductor memory device capable of adjusting internal... Semiconductor memory device capable of adjusting internal...

2001-03-20

2002-07-23

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06424593

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates a semiconductor memory device and more particularly, to a semiconductor memory device capable of adjusting an internal parameter after package molding.
2. Description of the Background Art
In recent years, requirements for not only a large capacity but also high speed of a semiconductor memory device have been piled up; an interfacing technique in a high frequency region largely exceeding 100 MHz has also been necessary in DRAM (Dynamic Random Access Memory). Under such circumstances, a possibility has been enhanced that variations in internal parameters of a chip caused by fluctuations in conditions for the fabrication process thereof exert adverse influences on an operation of a semiconductor memory device.
Especially, in a memory device with high speed, it has been important to reduce a variation in capacity added to a node (hereinafter referred to input capacitance as well) to which an external signal is input. Such a variation in input capacitance &Dgr;Cin leads to a change in delay between external signals caused when the signals are caught into the device. As a result, timings in generation of internal signals in the device in response to the external signals are different therebetween, and on this occasion, a possibility occurs that normal operation of the memory device cannot be performed in the entirety.
For example, in a memory device of a 100 MHz class, a precision of a level &Dgr;Cin=1.0 pF (1.0×10
−12
F) has been generally required with respect of a variation in input capacitance. With this level adjusted, an input capacitance has been sufficiently adjustable by fine tuning of a pattern of an aluminum wring layer following fabrication of a semiconductor chip. In memory device of a 800 MHz class, however, since timing specifications or setting-up and holding are strictly defined at a level of a system in which a DRAM is incorporated, a strict precision to a level &Dgr;Cin=50 fF (5.0×10
−14
F) is imposed on the input capacitance as requirement.
Adjustment of an input capacitance to such a strict precision is very hard to be achieved only by fine control of process conditions for the fabrication represented by pattern adjustment in a wring layer. This is because a variation in capacitance value caused by deformation such as of cable interconnects in resin encapsulation of a molding step cannot be neglected to satisfy a required precision; therefore, an input capacitance as designed is very hard to be achieved to such a level of precision.
Moreover, in a mas production stage, an input capacitance of each chip and an input capacitance at each pin of the chip are further varied by fluctuations in conditions for a fabrication process; therefore, control of variations in input capacitances has been very hard only by a design prior to the molding and control of the conditions for a fabrication process.
Furthermore, in a memory device requiring a high speed operation, a skew indicating a phase shift of an input/output signal from a reference clock has also been becoming an important specification.
FIG. 19
is a conceptual diagram representing a configuration performing data output in synchronism with a trigger clock.
In
FIG. 19
, for example, shown is a configuration in which data of 16 bits are output through 16 data terminals
200
-
0
to
200
-
15
. Data output buffers
210
-
0
to
210
-
15
are provided correspondingly to the respective data terminals
200
-
0
to
200
-
15
. The data output buffers output data to respective corresponding data terminals at a timing according to a trigger clock signal CLK transmitted from a clock buffer
220
.
Since the clock buffer
220
is shared by a plurality of data output buffers, there arises a shift in data output timing between a data output buffer in the central section close to the clock buffer
220
(for example,
210
-
7
or
210
-
8
) and a data output buffer far from the clock buffer
220
(for example,
210
-
0
or
210
-
15
) due to a difference in delay in propagation of a trigger clock therebetween and thereby, a problem occurs since a phase shift referred to as skew is generated. In a DRAM operating at high speed, since a data output cycle becomes shorter, none of such a skew will be able to be neglected.
Moreover, while in DRAM, holding data is required to be executed by a refresh operation, a cycle in which a refresh operation is performed (hereinafter simply referred to as refresh cycle) is largely related to power consumption of the entire DRAM. While a refresh cycle is set to a time length shorter than a cycle in which data holding can be ensured in DRAM, the refresh cycle is, on the other hand, set as long as possible and thereby, reduction in power consumption can be realized. Hence, in a high frequency DRAM having a tendency of increasing power consumption, it is an important technique to set a proper refresh cycle.
A data holding characteristic of DRAM, however, alters between before and after package molding step; therefore, a prior art method in which a refresh cycle is set by fuse blowing based on a test result in wafer test conducted in a chip state has had difficult performing fine setting of a refresh cycle.
Furthermore, in a memory, a word structure showing the number of bits of data which can be simultaneously input/output in one time addressing has been generally determined before the package molding according to whether a wring pattern or bonding is present or absent.
FIGS. 20A and 20B
are conceptual diagrams describing a prior art setting method for a word structure.
Referring to
FIGS. 20A and 20B
, a word structure is set according to whether coupling between a lead frame
230
coupled with a power source potential (ext.VCC) terminal
240
and a mode select terminal
250
are present or absent. In
FIGS. 20A and 20B
, shown are respective cases of no coupling and coupling between the mode select terminal
250
and the lead frame
230
.
FIG. 21
is a circuit diagram representing a configuration of a mode select circuit generating a mode select signal according to a coupling state of a mode select terminal.
Referring to
FIG. 21
, a mode select circuit
260
includes P type MOS transistors
252
and
254
coupled in parallel between a power source potential ext.VCC and a node N
0
, an N type MOS transistor
256
coupled between the node N
0
and a ground potential Vss, and an inverter
258
generating a mode select signal MSL according to a potential level of the node N
0
. A power-on reset signal/POR which is activated to L level for a prescribed period after power-on is input to the gate of the transistor
252
. A mode select terminal
250
is coupled to the gate of the transistor
256
.
Accordingly, as shown in
FIG. 20A
, when the mode select terminal
250
is not coupled to the lead frame
230
and in a floating state, the transistor
256
is not turned on, therefore, a potential level of the node NO goes to H level at a timing at which a power-on reset signal/POR is activated (to L level) and a mode select signal MSL is set to L level. Since the mode select signal MSL is input to the gate of the transistor
254
, L level of the mode select signal MSL is latched by the inverter
258
and the transistor
254
.
On the other hand, as shown in
FIG. 20B
, when a mode select terminal
250
is coupled with a lead frame
230
, a transistor
256
is turned on; therefore, a mode select signal MSL is set to H level if a power-on reset signal/POR is finally deactivated (to H level) even after the power-on reset signal/POR is activated (to L level) for a prescribed period following power-on.
In such a way, a mode select signal is set to H level or L level according to the presence or absence, respectively, of coupling between the mode select terminal
250
and the lead frame
230
. Hence, for example, when a signal level of a 2 bit mode select signal is defined using two mode select terminals, one of word structures of 2
2
=4 kinds, for example, one of ×4 bits/×

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