Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Reexamination Certificate
1996-11-15
2002-07-09
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
C345S182000, C345S182000
Reexamination Certificate
active
06417834
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an arrangement for graphically displaying IQ values of a demodulator for quadrature-amplitude-modulated signals.
An arrangement of this type is known (data sheet of the vector signal analyzer HP 89400-8 of the company Hewlett Packard). The IQ values emitted serially at the IQ output of the QAM demodulator are successively and intermediately stored in a data memory in the sequence of their occurrence, and can then be read out therefrom via a processor and graphically displayed on a video screen in the IQ plane (X-Y coordinate. plane). For this purpose, a data memory with a large storage capacity is required, e.g. for only 4096 signal statuses a 4 MB data memory is required (page 4 of the Hewlett Packard data sheet). Moreover, with this known arrangement possible errors. in the data transmission path between the transmitter and the receiver can be measured only in a complicated way.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an arrangement having a simple and economical construction, and which moreover enables a universal method of operation and evaluation of the IQ values.
In general terms the present invention is an arrangement for the graphic display, in the IQ plane on the screen of a display device, of the IQ values emitted at the output of a demodulator for quadrature-amplitude-modulated signals. The arrangement has a data memory and a processor that controls the display device. An address of the data memory is allocated to each individual IQ value and a pixel of the display device is allocated to each address of the data memory. Information allocated to the respective IQ value is stored under each address of this data memory. The processor is directly connected to the IQ output of the demodulator and is structured such that it determines the associated IQ value address in the data memory for each IQ value.
Advantageous developments of the present invention are as follows.
A predetermined pixel hold time is stored under each address of the data memory upon occurrence of the corresponding IQ value.
Under each address of the data memory is stored the frequency with which this address, and thereby the corresponding IQ value, has been determine din a predetermined acquisition time.
In the inventive arrangement, a separate address of the data memory is allocated to each individual digitized IQ value, and it is thereby possible to store separate information respectively for each individual pixel allocated to an IQ value. One possibility for this is that the desired pixel hold time is respectively stored under each address. Another possibility is to store under each address the frequency with-which this respective address, and thereby the associated IQ value, occurs within a predetermined acquisition time period. In addition to these two particularly advantageous possibilities, arbitrary additional information can also be stored under the respective addresses. This information. is taken into account during the display of a respective pixel, e.g. different brightnesses or different colors for the pixel display.
For an inventive arrangement, only one data memory with a relatively small memory capacity is required. For 8-bit quantized IQ values, for example, only one 65,536-word data memory is required. Nonetheless, with the inventive arrangement not only transmission-side errors of the modulator, such as IQ phase errors, IQ amplitude inequalities or, respectively, the carrier suppression, are measured, but errors of the transmission path between the transmitter and the receiver, e.g. the phase jitter, the sinusoidal interference, the signal-to-noise ratio or, respectively, the vector error magnitude (VEM), RMS and peak are also measured.
REFERENCES:
patent: 4630099 (1986-12-01), Rzeszewski
patent: 4631533 (1986-12-01), Mark, Jr.
patent: 5442646 (1995-08-01), Chadwick et al.
patent: 5479606 (1995-12-01), Gray
patent: 5612710 (1997-03-01), Christensen et al.
Hewlett Packard data sheets, Using Vector Modulation Analysis in the Integration, Troubleshooting and Design of Digital RF Communications Systems, Product Note HP 89400-8, pp. 1-28.
Lewis David L.
Rohde & Schwarz GmbH & Co. KH
Schiff & Hardin & Waite
Shalwala Bipin
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