Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-12-17
2002-05-14
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S520000, C257S513000
Reexamination Certificate
active
06388305
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits, and more specifically to semiconductor antifuses and methods for forming the same.
BACKGROUND OF THE INVENTION
To increase device yield, semiconductor integrated circuits such as DRAM and SRAM memories employ redundant circuitry that allows the integrated circuits to function despite the presence of one or more manufacturing or other defects (e.g., by employing the redundant circuitry rather than the original, defective circuitry). For example, conventional DRAM and SRAM memories often use laser fuse blow techniques as part of their redundancy scheme wherein redundant circuitry may be employed in place of defective circuitry by blowing one or more fuses with a laser beam.
While laser fuse blow techniques improve device yield, several problems remain. Laser fuse blow techniques must be performed at the wafer level and thus are time consuming and costly. For example, a wafer typically must leave a test station for fuses to be blown, and then returned to the test station for verification. For DRAM memories, post burn-in module yield loss can reach 80% due to single cell bit fails. However, while single cell fails are recoverable with redundancy, laser fuse blow techniques cannot be applied to modules. Device yield therefore remains low despite the use of laser fuse blow techniques. Accordingly, a need exists for improved techniques for implementing redundancy within semiconductor integrated circuits.
SUMMARY OF THE INVENTION
To address the needs of the prior art, novel electronically programmable elements or “antifuses” are provided which have relatively high resistances (e.g., a few Mohms or more) when unblown and relatively low resistances (e.g., a few kohms or less) when blown. Specifically, in a first aspect of the invention, a first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type (e.g., p-type) that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type (e.g., n-type); and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface of the trench and a conductive material filling the lined trench. The first logic element is configured (e.g., through selection of the doping level of the first layer, the type and thickness of the dielectric material, the type of conductive material (typically n+ doped polysilicon having a doping level of about 1×10
19
cm
−3
or greater), etc.) so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. Prior to breakdown, the first logic element has a high resistance (e.g., a few Mohms or more), and after breakdown, the first logic element has a low resistance (e.g., a few kohms or less).
In a second aspect of the invention, a second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface of the substrate and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface of the trench and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured (e.g., through selection of the doping level of the first layer, the type and thickness of the first dielectric material, the type of second dielectric material, the type of electrode, the type and thickness of the dielectric layer (typically an oxide, a nitrided oxide or an oxide-nitride-oxide stack having a thickness less than about 100 angstroms), etc., so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location. Prior to breakdown, the second logic element has a high resistance (e.g., a few Mohms or more), and after breakdown, the second logic element has a low resistance (e.g., a few kohms or less). Methods for forming the first and the second logic elements also are provided.
Because the first and the second logic elements are electronically programmable, the logic elements are well suited for use in redundant circuitry schemes. For example, the logic elements can be blown at the module level of a circuit design while a wafer remains at a test station. Both device yield and test throughput thereby are significantly increased.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.
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Bertin Claude L.
Hedberg Erik L.
Houghton Russell J.
Levy Max G.
Mohler Rick L.
DeLio & Peterson LLC
International Business Machines - Corporation
Owens Douglas W.
Reynolds Kelly M.
Thomas Tom
LandOfFree
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