Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Measuring or testing
Reexamination Certificate
2000-11-13
2002-05-07
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Measuring or testing
C324S1540PB, C327S144000
Reexamination Certificate
active
06385273
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89101615, filed Jan. 31, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a device for testing signals. More particularly, the present invention relates to a device for testing a clock pulse generating circuit.
2. Description of Related Art
In a digital system, operations are often carried out by referring to a clock signal. Without a normal clock pulse generator, synchronization with other sections of the circuit is impossible. Since clock signals are of such importance to a digital circuit, clock signal generating circuit is often the first component to be tested. In general, clock pulse generator is tested using a counter. The counter is capable of computing the frequency of clock pulse signal to detect any abnormality.
Due to rapid progress in semiconductor technologies, many digital circuits are integrated with a clock pulse generator on a silicon chip. Furthermore, by the addition of a phase lock loop in the clock pulse generator, any signal frequency can be obtained from a single quartz oscillator. However, testing the clock pulse generating circuit inside a highly integrated silicon chip is difficult. Nowadays, system having a clocking frequency in excess of 100 MHz is quite common. As the operating speed of a digital system continues to increase due to the development of advance techniques, a counter capable of testing high frequency clock pulses is needed to check the performance of the system.
To test the clock pulse generating circuit of a digital system, a special counter is conventionally required, and the test cost is high. This type of testing is unsuitable for highly integrated silicon chip. Moreover, as operating speed of the system is increased, frequency response of the counter has to be increased. Hence, testing equipment has to be upgraded resulting in a higher production cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a testing device that permits an external tester to check the clock pulse generating circuit in a digital system.
A second object of this invention is to provide a testing device capable of checking the signals from a clock pulse generator together with a simple external tester. Since additional counter is not needed, production cost is lowered.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a testing device for checking a clock pulse generating circuit. The clock pulse generating circuit includes an oscillator and an analog phase lock loop (APLL) circuit. The oscillator outputs a first signal to the APLL circuit. The APLL circuit multiplies the frequency of the clock signal by a preset value to produce a multiplied clock signal. The testing device includes a reset circuit, a dividing unit and a mask circuit.
A first reset signal and the clock signal are sent to the reset circuit, and then a second reset signal that also synchronizes with the first signal is generated by the reset circuit. The dividing unit and the mask circuit are controlled by the second reset signal. When the second reset signal is activated, the dividing unit and the mask circuit are reset.
The multiplied clock signal is picked up by the dividing unit and then the multiplied clock signal is divided by an integral multiple to produce a divided clock signal. The divided clock signal is output to the mask circuit. The initial and end of the active section of the divided clock signal is masked by the mask circuit to produce a masked clock signal.
According to one preferred embodiment of this invention, the masked clock signal is transferred to a tester. Cycle width of the masked clock signal is computed inside the tester, and the first reset signal is produced by the tester.
The reset circuit includes a first flip-flop and a second flip-flop. The first flip-flop and the second flip-flop both have a data input terminal, a clock pulse input terminal and a state output terminal. The clock pulse input terminal of the first and the second flip-flop receives the clock signal. The data input terminal of the first flip-flop receives the first reset signal. The data input terminal of the second flip-flop is connected to state output terminal of the first flip-flop. The state output terminal of the second flip-flop outputs the second reset signal.
The dividing unit includes a plurality of flip-flops. Each flip-flop has a data input terminal, a clock pulse input terminal, a state output terminal and a complementary state output terminal. The complementary state output terminal is coupled to the data input terminal for each flip-flop. The flip-flops are serially connected. The state output terminal of the previous flip-flop is coupled to the clock pulse input terminal of following flip-flop. The clock pulse input terminal of the first flip-flop receives the multiplied clock signal while the state output terminal of the last flip-flop outputs the divided clock signal.
Furthermore, each one of the flip-flops inside the dividing unit has a reset input terminal. Each reset input terminal is controlled by the second reset signal. When the second reset signal activates, each flip-flop inside the dividing unit is reset.
According to this invention, the mask circuit blankets an initial portion within the active section of the divided clock signal. The masked initial portion has a length equal to two cycle periods of the first signal. In addition, the mask circuit also blankets an end portion of the active section of the divided clock signal. The masked end portion also has a length equal to two cycle periods of the first signal.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a testing method. The testing method is designed for testing a clock pulse generating circuit which outputs a clock signal and a multiplied clock signal. The testing method comprises the steps of (1) generating a second reset signal in synchrony with the clock signal by receiving a first reset signal; (2) dividing the multiplied clock signal to produce a divided clock signal, wherein the divided clock signal is reset when the second reset signal is activated; (3) masking uncertain portions of the divided clock signal to produce a masked clock signal, wherein the masked clock signal is reset when the second reset signal is activated; and (4) determining the correctness of the clock signal according to the masked clock signal.
According to one preferred embodiment of this invention, the cycle width of the masked clock signal is computed after the first reset signal is issued, in order to determine the correctness of the clock signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6172544 (2001-01-01), Sugamori
patent: 6219305 (2001-04-01), Patrie et al.
Chuang Ying-Lang
Hsiao Chu-Yu
Hsu Ming-Hsun
J.C. Patents
Lam Tuan T.
Via Technologies Inc.
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