Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-06-27
2002-05-21
Sherry, Michael J. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010, C257S048000, C438S018000
Reexamination Certificate
active
06392434
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor testing, and more particularly, to an improved method of finding causes of wafer defects by determining failure modes that have greater influence over the yield rate.
BACKGROUND OF THE INVENTION
Semiconductor wafer fabrication involves complex manufacturing processes to produce integrated circuits on the surface of silicon wafers. To ensure the quality of the integrated circuit chips, various testing methods have been devised to find defects on the wafer in order to improve the manufacturing processes. One method is to place testing circuitry at various locations on the wafer, and use test signals to determine the functionality of the circuitry. Typically, the testing circuit is designed into the chips on the wafer, and testing pads are made alongside the chips to allow probe pins to insert testing signals and measure the response signals. The chips are characterized as functional chips or defective chips according to these response signals. The defective chips are mapped on the wafer to create defect wafer maps. Typically, an experienced engineer then analyzes the defect wafer maps to determine the root cause of the defects. For example, a defect wafer map with defect patterns having curvilinear features may resemble a mechanical scratch; the defect patterns characterized by a grouping of low-density, sparse structures into amorphous clusters might resemble the trail off of a teardrop shaped stain.
Different types of electrical tests (such as direct current test, functionality test, etc.) may be conducted on the chips. For each type of test, the chips that fail the test are deemed defective, and may be marked on a map of the wafer to generate a defect wafer map. When an error occurs in a particular processing step or equipment, the defects caused by that error tend to concentrate on a particular region on a wafer. Thus, a process engineer may determine the cause of the defects by examining the wafer maps and analyzing the regions having a concentration of defects. Because hundreds of wafers are produces each day in a semiconductor plant, and many types of failure signatures need to be analyzed, an automated process of analyzing wafer maps to enable a user to quickly determine the cause of the wafer defects is desired.
The present invention is directed to an improved method of analyzing wafer maps to facilitate determination of the cause of defects on semiconductor wafers by analyzing defect density in different regions of the wafers and generating graphical comparison charts.
REFERENCES:
patent: 5576554 (1996-11-01), Hsu
patent: 5585737 (1996-12-01), Shibata
patent: 5818249 (1998-10-01), Monohara
patent: 6124142 (2000-09-01), Fujino
patent: 6232134 (2001-05-01), Farber
Blakely , Sokoloff, Taylor & Zafman LLP
Nguyen Trung
ProMOS Technologies Inc.
Sherry Michael J.
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