Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-01-05
2002-04-30
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330, C711S163000
Reexamination Certificate
active
06381175
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to storage devices and more particularly to a method and system for validating flash memory.
BACKGROUND OF THE INVENTION
Flash memory is one type of non-volatile memory. A non-volatile memory retains its state after power has been terminated to the memory. A flash memory cell incorporates a floating gate with a sector, or group of flash memory cells, sharing a common control gate. Because a sector of flash memory cells shares a common control gate individual cells may not be erased. Rather a sector of cells is erased all at once. Erasing a sector of flash memory cells occurs by applying an erase pulse and measuring the threshold voltage of each memory cell until all cells have a threshold voltage below a certain level; all of the cells have not been erased until they all have a threshold voltage below a certain level. A problem with this procedure is that some cells may go into depletion (the threshold voltage is set too low) while the other memory cells are being erased. When a memory cell in a sector of flash memory is driven into depletion, no cell on the same bit line may be read because a depleted cell will source current, causing all bits in the sector to appear to store a “one” (indicating an erased bit).
To address this problem, some implementations of flash memory utilize algorithms as part of an erase procedure to confirm no bits are in depletion. If any bit is depleted, an algorithm is executed to correct the problem. These algorithms are referred to as a “compaction verify” algorithm and a “compaction” algorithm. A “compaction verify” algorithm determines the amount of current on a bit line after a sector is erased. A depleted bit is present if there is current on the bit line. Once it is determined that there is a depleted bit in a sector, the “compaction” algorithm executes. The compaction algorithm identifies the bit with a threshold voltage that is too low and corrects the voltage. These two algorithms are conventionally implemented as part of an erase command to verify that erasure has been performed properly.
A problem with the above-described procedure for ensuring flash memory cells are not depleted is that power may be terminated during an erase process before the “compaction verify” and “compaction” algorithms are executed. Therefore, it is possible that bits of flash memory will be in depletion upon powering up the memory. According to the above-described conventional systems, the problem is discovered only after data are unsuccessfully read from or written to a sector having the depleted bit, resulting in a system fault or interrupt.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved method and system for validating flash memory. The present invention provides a system and method for validating flash memory that addresses shortcomings of prior systems and methods.
According to one embodiment of the invention, a method for validating flash memory includes selecting for execution and executing, from a plurality of setup procedures available for the memory, a memory validation setup procedure setting respective values for a plurality of parameters that are also parameters set by execution of the other of the plurality of setup procedures. The method also determining that validation of a particular sector of the flash memory is desired. In response the particular sector of the flash memory is validated, including examining the values of the plurality of parameters.
According to another embodiment of the invention, a flash memory module includes a flash bank, comprising a plurality of sectors of flash memory, and a flash memory control circuit. The flash memory control circuit comprises a flash state machine. The flash state machine is used for controlling a plurality of operations on the flash memory. The flash state machine comprises a stand-by unit for monitoring the state of at least one variable, and initiating execution of a particular one of a plurality of setup units in response to the state of the at least one variable. The flash state machine also includes an execution unit operable to selectively perform each of the plurality of operations in response to the state of the plurality of parameters, including validating a designated sector of the flash memory. The flash state machine also includes a validation setup unit operable to set the plurality of parameters such that the execution unit validates a designated portion of the flash memory. The flash state machine also includes a plurality of additional setup units, each operable to set the plurality of parameters such that the execution unit performs a respective one of the plurality of operations.
Embodiments of the invention provide numerous technical advantages. For example, in one embodiment of the invention, a procedure is provided for validating portions of flash memory, which may be improperly erased due to a power failure or inadvertent reset. The validation procedure may be executed by a host upon start-up or at other suitable times without first executing an erase command. A device incorporating such a validation procedure is less susceptible to system interrupts and therefore is more reliable. Furthermore, embodiments of the invention incorporate existing procedures, resulting in improved flash memory with little additional circuitry and expense.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5751637 (1998-05-01), Chen et al.
patent: 6172906 (2001-01-01), Estakhri et al.
Brady III Wade James
Hoang Huan
Holmbo Dwight N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Method and system for validating flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for validating flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for validating flash memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2856760