Semiconductor integrated circuit having circuit for writing...

Details Semiconductor integrated circuit having circuit for writing... Semiconductor integrated circuit having circuit for writing...

2000-05-22

2002-01-22

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030

Reexamination Certificate

active

06341100

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which accepts serial data in synchronization with a clock signal and writes the data in a memory cell as parallel data. In particular, the present invention relates to a technique for performing a write operation at higher speed.
2. Description of the Related Art
These kinds of semiconductor integrated circuits having been developed include FCRAMs (Fast Cycle RAMs). FCRAMs are divided into two types. One type has an SDRAM like (Synchronous DRAM) interface for accepting data in synchronization with the rises of a single-phase clock signal. The other has a DDR SDRAM like (Double Data Rate SDRAM) interface for accepting serial data in synchronization with the respective rises of complementary clock signals (or in synchronization with both the rises and falls of a single-phase clock signal). The general outlines of FCRAMs are described in NIKKEI ELECTRONICS 1998.6.15 (no. 718), Nikkei business publications.
FIG. 1
shows the main parts associated with a write operation in the FCRAM with an SDRAM like interface. The FCRAM has an input controlling unit
1
, a core timing controlling unit
2
, a core controlling signal generating unit
3
, and a memory core unit
4
as the circuit associated with the write operation.
The input controlling unit
1
has a clock buffer
5
, an input buffer
6
, a command decoder
7
, an RASZ generator
8
, a serial/parallel controlling circuit
9
, a DQ buffer
10
, and a serial/parallel conversion circuit
11
.
The clock buffer
5
receives a clock signal CLK from the exterior, and outputs an internal clock signal ICLKZ. The input buffer
6
accepts a command signal CMD in synchronization with the internal clock signal ICLKZ, and outputs the accepted signal as an internal command signal ICMD. The command decoder
7
receives the internal command signal ICMD, decodes the command, and outputs a command activating signal ACTZ. The RASZ generator
8
receives the command activating signal ACTZ and a self-precharging signal SPRZ, and outputs a basic signal BRASZ for controlling circuit associated with row addressing. The serial/parallel controlling circuit
9
receives the internal clock signal ICLKZ, and outputs a write switching signal WSWZ. The DQ buffer
10
sequentially receives serial data signals DQ in synchronization with the internal clock signal ICLKZ and outputs the received signals as internal data signals DI
0
and DI
1
. The serial/parallel conversion circuit
11
accepts the internal data signals DI
0
and DI
1
in synchronization with the write switching signal WSWZ and respectively outputs the accepted signals as common data signals CDB
0
Z and CDB
1
Z.
The core timing controlling unit
2
has a BLT activating timing generator
12
, a word line activating timing generator
13
, an SA activating timing generator
14
, and a CL activating timing generator
15
.
The BLT activating timing generator
12
receives the basic signal BRASZ , the write switching signal WSWZ, and a word line inactivating signal WLRZ, and outputs a bit line activating signal BLSZ and a bit line inactivating signal BLRZ. The word line activating timing generator
13
receives the bit line activating signal BLSZ and the basic signal BRASZ, and outputs a word line activating signal WLSZ and the word line inactivating signal WLRZ. The SA activating timing generator
14
receives the word line activating signal WLSZ and the word line inactivating signal WLRZ, and outputs a sense amplifier activating timing signal BLEZ. The CL activating timing generator
15
receives the sense amplifier activating timing signal BLEZ, and outputs a column line activating signal BCLZ and the self-precharging signal SPRZ.
The core controlling signal generating unit
3
has a BLT generator
16
, a main-word decoder
17
, a sense amplifier controller
18
, and a column decoder
19
.
The BLT generator
16
receives the bit line activating signal BLSZ and the bit line inactivating signal BLRZ, and outputs bit line controlling signals BLTX, BLTZ and a bit line controlling signal BRSX for precharging bit lines BL, /BL. The main-word decoder
17
receives the word line activating signal WLSZ and the word line inactivating signal WLRZ, and output a word line signal WLZ. The sense amplifier controller
18
receives the sense amplifier activating timing signal BLEZ, and outputs sense amplifier activating signals LEX and LEZ. The column decoder
19
receives the column line activating signal BCLZ, and outputs a column line signal CLZ.
The memory core unit
4
includes sense amplifiers
20
, memory cells
21
, and other components. The memory core unit
4
receives the bit line controlling signals BLTX, BLTZ, and BRSX, the word line signal WLZ, the sense amplifier activating signals LEX and LEZ, the column line signal CLZ, and the common data signals CDBOZ and CDB
1
Z.
Of the signals described above, those with trailing “z” are positive logic signals, and those with trailing “X” are negative logic signals. Incidentally, address signals are omitted from FIG.
1
. In actual device, the above-described circuits are activated in accordance with address signals, thereby selecting a predetermined memory cell.
FIG. 2
shows the main parts of the memory core unit
4
.
The memory core unit
4
has plural pairs of complementary bit lines BL and /BL. The bit lines BL are connected with one another through nMOSs
4
a
and
4
b
. The bit lines /BL are connected with one another through nMOSs
4
c
and
4
d
. The bit lines BL and /BL are connected to nMOSs
4
e
and
4
f
for equalizing, nMOSs
4
g
and
4
h
for precharging, column switches
4
i
and
4
j
each consisting of an nMOS, a sense amplifier
20
, and a memory cell
21
.
The gates of the nMOSs
4
a
and
4
c
receive the bit line controlling signal BLTX. The gates of the nMOSs
4
b
and
4
d
receive the bit line controlling signal BLTZ. The gate of the nMOS
4
e
receives the bit line controlling signal BLTZ, and the gate of the nMOS
4
f
receives the bit line controlling signal BLTX.
Either the sources or the drains of the nMOSs
4
g
and
4
h
are connected to the bit lines BL and /BL, respectively. The others are connected to a precharging line VPR. The gates of the nMOSs
4
g
and
4
h
receive the bit line controlling signal BRSX.
Either the sources or the drains of the column switches
4
i
and
4
j
are connected to the bit lines BL and /BL, and the others are connected to data signals LDBX and LDBZ, respectively. The gates of the column switches
4
i
and
4
j
receive the column line signal CLZ. The data signals LDBX and LDBZ are complementary signals. The data signal LDBZ and the data signal LDBX carry the same logic as and the inverted logic from that of the common data signal CDB
0
Z, respectively. Other data signals LDBZ and LDBX (not shown) have the same logic as and the inverted logic from that of the common data signal CDB
1
Z, respectively.
The sense amplifier
20
has a CMOS inverter consisting of a PMOS
20
a
and an nMOS
20
b
, a CMOS inverter consisting of a pMOS
20
c
and an nMOS
20
d
, and a PMOS
20
e
and an nMOS
20
f
connected to the respective sources of the CMOS inverters to provide power supply thereto. The inputs and outputs of the CMOS inverters are connected to each other, and the respective outputs are connected to the bit lines /BL and BL. Either the source or the drain of the pMOS
20
e
is connected to the sources of the pMOS
20
a
and the pMOS
20
c
, and the other is connected to a power supply line VII. The gate of the pMOS
20
e
receives the sense amplifier activating signal LEX. Either the source or the drain of the NMOS
20
f
is connected to the sources of the nMOS
20
b
and the NMOS
20
d
, and the other is connected to a ground line VSS. The gate of the nMOS
20
f
receives the sense amplifier activating signal LEZ.
The memory cell
21
consists of an nMOS
21
a
for data transfer and a capacitor
21
b
. The gate of the nMOS
21
a
receives the word line signal WLZ.
Next, the operati

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