High-speed, low power, medium resolution analog-to-digital...

Details High-speed, low power, medium resolution analog-to-digital... High-speed, low power, medium resolution analog-to-digital...

2001-01-17

2002-05-28

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000, C341S118000, C341S159000, C341S122000

Reissue Patent

active

RE037716

ABSTRACT:

FIELD OF INVENTION
This invention pertains in general to analog-to-digital converters and in particular to analog-to-digital converters having a very high operating clock frequency, small die size, and low power consumption and methods of stabilizing the same against drift.
BACKGROUND OF THE INVENTION
Conventional high-speed analog-to-digital converters (“ADCs”) commonly employ a full flash architecture in which the analog-to-digital conversion is done in parallel by using approximately 2
n
voltage comparators.
FIG. 1
illustrates a conventional full flash ADC
100
including an input voltage
110
, a reference voltage
112
, a number of resistors, of which resistor
114
is representative, a number of conventional comparators, of which comparator
116
is representative, and a conventional decoder
118
that produces a multi-bit digital output
120
.
As is well known in the art, input voltage
110
is applied simultaneously to each comparator
116
. In addition, fractional portions of the reference voltage
112
are applied to the comparators
116
by dividing the reference voltage
112
in equal increments (or thresholds) by the resistors
114
. The output of each comparator
116
is applied to the decoder
118
which decodes such received inputs into a multi-bit digital output
120
representative of the input voltage
110
. Although a single-ended structure is shown in FIG.
1
and throughout this discussion, in practice a fully differential structure can be used.
ADCs for operation at high frequencies, however, require a large amount of integrated circuit area and have high power consumption, and all such requirements increase as the number of bit of resolution of the ADC increases. For example, a 6-bit full flash ADC requires about 2
6
=64 voltage comparators. In a CMOS implementation of a full flash ADC, these comparators are normally implemented using conventional auto-zero voltage comparators. An auto-zero voltage comparator, however, requires a two-phase clock for auto-zeroing in the first phase, and for actual signal comparison in the second phase. Unfortunately, such two-phase design limits the maximum achievable operating frequency to a factor of two lower than otherwise possible, other factors being equal, if non-auto zero voltage comparators are employed.
Non-auto zero voltage comparators, such as those used in full flash ADCs implemented in Bipolar or BiCMOS integrated circuit processes, are generally not practical for implementation in standard CMOS processes because device mismatches (e.g., input offset voltage) of CMOS voltage comparators tend to be much higher than for Bipolar equivalents. CMOS voltage comparators with low input offset voltage can usually only be obtained using complex circuitry that requires large integrated circuit area with associated higher power consumption, and generally lower conversion speed.
Therefore, it is desirable to provide a high resolution ADC that has small die size and low power consumption, and that avoids the effects of operational mismatches.
SUMMARY OF THE INVENTION
Accordingly, the full flash ADC of the present invention includes a plurality of comparators and a referencing scheme that effectively cancels out the input offset voltages of the comparators. The input offset voltage of each of the plurality of comparators is obtained by performing a self calibration process on the ADC during, for example, power up. Then, the input offset voltage for each of the comparators is stored in a look-up table. When the ADC is used, the look-up table provides offset correction to the normal reference voltages for each comparator.
In one embodiment of the present invention, the offset look-up table controls a digital-to-analog converter (“DAC”). In addition, a track/hold (“T/H”), circuit, also known as a sample/hold circuit, is connected to a reference input of each comparator. The T/H circuit receives its input from the DAC and holds received voltages for application to its associated comparator as a first or reference input. Each comparator receives the analog input voltage as its second input and the outputs of the comparators are supplied a conventional decoder.
The look up table, in combination with a T/H controller and the DAC, operates each T/H circuit to provide a voltage equivalent to the reference voltage corrected by the input offset voltage of the associated comparator. After the correct reference voltages are loaded into the T/H circuits, the analog input signal is applied to all of the comparators. Each comparator produces an output signal indicating whether the magnitude of the input signal is, for example, greater than the magnitude of the corrected reference voltage. The decoder receives such comparator outputs and decodes the outputs into a representative multi-bit digital output signal.


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