On-chip higher-to-lower voltage input stage

Details On-chip higher-to-lower voltage input stage On-chip higher-to-lower voltage input stage

2001-01-19

2002-04-23

Zweizig, Jeffrey (Department: 2818)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S077000

Reexamination Certificate

active

06377105

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ‘on-chip’ higher-to-lower voltage input stage. More particularly, the present invention relates to an input stage, incorporated as part of a monolithic integrated circuit, that is capable of carrying out voltage level conversion where the input voltage to the input stage is capable of exceeding at least one of the voltages applied to the input stage's voltage supply rails.
2. Background Art
FIG. 1
illustrates a known circuit for translating one voltage to another voltage.
This circuit
100
comprises two n-type MOS transistors MN
1
and MN
2
operatively arranged to form what is commonly referred to as a ‘source follower’; so called since the voltage appearing on the source terminal of transistor MN
1
tracks, or follows, that which is applied to its gate terminal. Transistor MN
1
has its drain terminal connected to a positive supply rail VDD, its source terminal
110
is connected to the drain and gate terminals of transistor MN
2
and its gate control terminal
120
receives a first voltage V
1
. Transistor MN
2
has its source connected to the supply rail VSS. An output voltage Vout, which is derived from the first voltage V
1
, appears at the common connection
110
between transistors MN
1
and MN
2
. Transistor MN
2
is a diode connected transistor and therefore acts as an active resistor, alternatively transistor MN
2
can be considered as acting as a current source.
A circuit
100
such as that shown in
FIG. 1
is used in analogue circuit designs and one application is a voltage divider. If such a circuit
100
were to be used as an input stage of an integrated circuit it would incorporate additional circuitry for protection against Electro-Static Discharge (ESD): such ESD protection shall be described in more detail in relation to FIG.
2
.
FIG. 2
illustrates a known CMOS inverting stage
200
.
The inverting stage
200
, including its Electro-Static Discharge protection diodes D
1
and D
2
, which would typically be seen at an input pin of a digital integrated circuit (not illustrated), comprises p-type and n-type transistors MP
3
and MN
3
.
Transistor MP
3
has its source terminal connected to a positive supply rail VDD, its respective drain and gate terminals
210
,
220
are connected to the respective drain and gate terminals of transistor MN
3
. Transistor MN
3
has its source connected to the supply rail VSS. The respective input and output voltages Vin, Vout of the stage appear at the respective common gate and drain terminals
220
,
210
of transistors MP
3
and MN
3
.
Diode D
1
has its anode connected to the supply rail VSS and its anode connected to the gate terminal
220
. Diode D
2
has its anode connected to the gate terminal
220
and its cathode connected to a supply rail VDD.
It should be noted that when the input voltage Vin exceeds the supply voltage VDD, diode D
2
would act to clamp the input voltage Vin to a value of approximately VDD+VD: where VD is the forward voltage drop of a diode. Such clamping would be an undesirable effect and disadvantageous to an ‘on-chip’ higher-to-lower voltage input stage.
As the semiconductor process technologies advance the reduction in the geometry's of transistors, and hence the overall size of integrated circuits, also leads to a reduction in the supply voltages which in turn leads to lower power, more efficient electronic circuits, systems and apparatus. For a number of years the supply voltage for many integrated circuits remained, and still remain, at 5 volts. However, due to the advances in process technology these supply voltages are being driven down to lower values. For example, 5 volt CMOS circuits are being replaced with circuits that operate on approximately 2 and 3 volt technology. Therefore, there is a need for an ‘on-chip’ higher-to-lower voltage input stage that will allow 5 volt and 3 volt technology, for example, to be interfaced without the need of costly external circuits and components.
Therefore, due to the aforementioned disadvantage and associated problems in relation to a need for an interface between such 2/3 volt and 5 volt technologies, for example, solutions have been proposed. One such proposal in the form of a circuit which is taught in the U.S. Pat. No. 5,151,619 to Austin et al., which is herein incorporated by reference. However, there is an associated problem associated with the circuit of U.S. Pat. No. 5,151,619 in that it is an ‘off-chip’ solution and as such it increases the component count and complexity, size and the cost of a system employing such an arrangement.
OBJECTS & SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide circuitry that overcomes the aforementioned problems and/or disadvantages.
Another object of the present invention is to provide a circuit that is tolerant of an input voltage that exceeds at least one of its voltage supply rails.
Another object of the present invention is to provide a circuit that can be used as a x to y volt level translator, where the magnitude of x is greater than that of y.
Another object of the present invention is to provide a level translator circuit that is input voltage tolerant and that can be incorporated within a monolithic analogue and/or digital integrated circuit.
In order to achieve these objects, the present invention proposes an input stage of an integrated circuit that comprises: first and second voltage dividers
305
,
305
′; and a comparator
325
; said first and second voltage dividers, which are operatively connected between second positive and negative voltage supply rails VDD, VSS, respectively receiving an input and reference voltage Vin, Vref and respectively providing first and second outputs voltages Vout
1
, Vout
2
, said output voltages being input to the comparator, which is operatively connected between said second voltage rails, for providing a third output voltage Vout
3
, said input voltage being supplied on an input terminal
320
by first circuitry
330
, that is supplied from first positive and negative voltage supply rails VH, CL, wherein the input voltage can pass beyond a voltage applied to at least one of the second voltage supply rails.
According to another embodiment of the present invention, the voltage dividers each comprise an MOS type transistor and a current source CS
1
, CS
1
′ that are operatively connected in series between said second positive and negative voltage supply rails, the gate
320
of said transistor of said first voltage divider being responsive to the input voltage, the gate
320
′ of said transistor of said second voltage divider being responsive to the reference voltage, the current sources of said respective first and second voltage dividers being responsive to their respective output voltages.
According to another embodiment of the present invention the input terminal is operatively connected to second circuitry D
1
, D
2
for operatively protecting the input stage against electrostatic discharge, said second circuitry being operatively connected between the first positive voltage supply rail and the second negative voltage supply rail.
According to another embodiments of the present invention the first and second negative voltage supply rails are connected together and the MOS transistors MN
1
, MN
1
′ are n-type MOS transistors having their drain terminals connected to the second positive voltage supply rail and their source terminals connected to the second negative voltage supply rail via their respective first and second current sources.
According to another embodiment of the present invention the input voltage is capable of increasing beyond a voltage applied to the second positive voltage supply rail.
According to another embodiment OLD the present invention the first and second negative voltage supply rails are at a voltage substantially equal to the ground potential of the input stage and the first and second circuitry and the second positive voltage supply rail is at a voltage less than

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