Phase-difference detector and clock-recovery circuit using...

Details Phase-difference detector and clock-recovery circuit using... Phase-difference detector and clock-recovery circuit using...

1999-06-07

2002-07-16

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

C375S376000, C375S374000, C375S375000

Reexamination Certificate

active

06421404

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-difference detector used for a PLL (phase-locked loop), which can be applied to optical communication or the like.
This application is based on Patent Application No. Hei 10-160045 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In a serial communication system such as an optical communication system, it is necessary to extract a clock component (or signal) from a serial data sequence at the receiving side, so as to receive data based on the extracted clock signal. The circuit for extracting a clock signal from a serial data sequence is called a clock-recovery circuit, which is a very important element for realizing an LSI used for the serial communication. This clock-recovery circuit is a kind of PLL, and can be generally realized using the structure shown in FIG.
6
.
In
FIG. 6
, reference symbol PD indicates a phase-difference detector, which detects a phase difference between a clock signal output from the VCO (voltage-controlled oscillator) and an input data-signal sequence, and determines whether the current phase is advanced or delayed and outputs the determined results as phase-difference signals. The phase-difference signals, a set of pulse signals whose pulse widths are proportional to each phase difference, are output from the “down” terminal and the “up” terminal at the output side. In this clock-recovery circuit, these “down” and “up” signals are fed back (as an input signal) via a charge-pump circuit and a low-pass filter into the VCO, so that the phase of the extracted clock signal corresponds to that of the data input signal.
An example circuit of the conventional phase-difference detector is shown in FIG.
7
. This circuit is disclosed by C. R. Hogge in “A Self Correcting Clock Recovery Circuit”, IEEE Transactions on Electron Devices, Vol. ED-32, No. 12, pp. 2704-2706, December, 1985.
FIG. 8
is a timing chart showing the operations of the circuit of FIG.
7
. This circuit comprises a flip-flop circuit FF
1
into which a signal is input at (timing corresponding to) a rising edge of the clock signal, another flip-flop circuit FF
2
which operates at (timing corresponding to) a decaying (or falling) edge of the clock signal, and two exclusive OR circuits XOR
1
and XOR
2
.
The exclusive OR between the data input signal “din” and the output of FF
1
is calculated so as to detect a phase difference between the clock signal and the data input signal, and a pulse signal whose pulse width corresponds to the detected phase difference is output from the “up” terminal. On the other hand, when a pulse signal is output from the “up” terminal, a pulse signal whose pulse width corresponds to half of the clock period is output from the “down” terminal.
As shown in the section from 3.0 ns to 4.0 ns in the horizontal axis in
FIG. 8
, when the difference between the rise timing of the clock signal and the transition timing of the data input signal becomes half of the clock period, the pulse width of the signal from the “up” terminal is half of the clock period. Therefore, the circuit as shown in
FIG. 7
can detect the phase difference, and can be applied to the PD in
FIG. 6
, thereby realizing a clock-recovery circuit.
The circuit in
FIG. 7
also has a data-recovery function for receiving and outputting data based on the extracted clock signal. That is, both (i) detection of the phase difference between the input data sequence and the extracted clock signal and (ii) data-receiving operation can be executed using the circuit of
FIG. 7
; thus, the structure of the LSI used for a communication system can be simplified.
However, in the phase-difference detector as shown in
FIG. 7
, a clock signal whose frequency can agree with the frequency of the data input signal (i.e., the data rate) is necessary. That is, as shown in the timing chart of
FIG. 8
, if the transition (between the high level and the low level) of the data input signal appears with a minimum period of 0.25 ns (see the section between 3 ns to 4 ns in FIG.
8
), then the period of the clock signal must also be 0.25 ns. Here, each “transition” of the data input signal corresponds to a period from a rise to a decay (or fall) of the data input signal, or to a period from a decay to a rise of it.
Here, the period of the high level or the low level of the clock signal is 0.125 ns, that is, half of the clock period. Therefore, the clock signal must maintain a frequency two times as high as the data rate.
This requirement causes a serious problem, in particular, in a circuit design aimed at high-speed operations using the maximum efficiency of each device to be used. The possible frequency of the clock signal to be generated and divided is basically determined depending on the efficiency or performance of the device; thus, in the conventional circuit such as the above, the possible data rate is half or less of the device efficiency.
In order to solve the above problem, a circuit for receiving data using both the rising edge and the decaying edge of the clock signal is used for receiving a high-speed data input signal. A sample circuit is shown in FIG.
9
. The data input signal input from the terminal “din” is distributed into two lines. The data signal received at the decay timing of the clock signal is output from terminal “dout0”, while the data signal received at the rise timing of the clock signal is output from terminal “dout1”. In this circuit, a clock signal whose frequency is half that of the data rate of the data input signal can be used. For example, a data input signal of 4 Gbps can be received using a clock signal of 2 GHz. That is, by using a device having the same performance as that used in the circuit of
FIG. 7
, high-speed operations at a frequency twice as high as that of the circuit of
FIG. 7
can be expected. In addition, a plurality of the circuits as shown in
FIG. 9
can be connected in a “tree” form and the frequency of the clock signal of each circuit can be half of the frequency of the clock signal of the previous circuit, thereby constructing a multi-bit output demultiplexer having a simple structure.
However, in the circuit as shown in
FIG. 9
, two distributed output signals are obtained with respect to a data input signal. In this case, accurate phase-difference information cannot be obtained only by simply calculating the exclusive OR between the data input signal and the output signal from the flip-flop circuit as calculated in the circuit of FIG.
7
. The reason for this is as follows. In the circuit of
FIG. 7
, the data signal is always obtained from the output of flip-flop FF
1
; however, the circuit of
FIG. 9
has different operations. For example, a data input signal which existed at each even-numbered position in the original serial data-signal sequence is output from FF
1
, while a data input signal which existed at each odd-numbered position in the original serial signal sequence is output from FF
3
. Therefore, even if the output of the “din” terminal thorough which all data passes and the output of FF
1
which includes only half of the information of the data are simply compared, phase-difference information as obtained by the circuit of FIG.
7
. cannot be generated in this case.
Accordingly, if the binary-tree type high-speed and simple structure as shown in
FIGS. 9 and 10
is applied to the demultiplexer which needs the highest operational frequency so as to operate it at the highest speed, then a separate phase-difference detector is also necessary.
SUMMARY OF THE INVENTION
In order to realize a high-speed serial communication circuit, an objective of the present invention is to provide a phase-difference detector which can use a clock signal whose frequency is half of the data rate, receive data at both rise timing and decay timing of the clock signal, and output phase-difference information between the data input signal and the clock signal.
Therefore, the present invention provides a phase-difference detector

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