Semiconductor package and enhanced FBG manufacturing

Details Semiconductor package and enhanced FBG manufacturing Semiconductor package and enhanced FBG manufacturing

2000-01-04

2002-07-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S127000, C257S678000, C257S692000, C257S693000, C257S701000, C029S831000, C029S840000, C361S761000, C361S762000, C361S795000, C361S707000

Reexamination Certificate

active

06420207

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to hybrid electronics, and more particularly, to improving electrical and mechanical connectivity to semiconductor packages.
2. Related Art
Semiconductor packages are known by a variety of generic names, such as ball grid arrays (BGA), plastic ball grid arrays (PBGA), multi chip module-laminates (MCM-L), and packaging substrates. Semiconductor packages can be composed of any one of a variety of materials, such as bismaldehyde trizaine resins, multifunctional epoxy resins, polyamide systems, and a range of other materials. The base materials used to manufacture the substrate, also referred to as a laminate, are usually a combination of resin systems and woven fiberglass.
A semiconductor package typically is manufactured by taking a substrate and depositing a metallization layer to develop circuitry for a wire bond area on one side and circuitry for a ball attach area on the opposite side of the substrate. Solder masks can be applied to provide mechanical and electrical support, and a via hole or through hole connects the wire bond circuitry to the ball attach circuitry.
Semiconductor packages serve as a mounting device for semiconductors. When a semiconductor is mounted on a semiconductor package, the semiconductor is usually a bare die. However, in certain instances, the bare die may be housed in some type of subassembly, which is in turn attached to the semiconductor package.
Semiconductor packages are actually interposers, which lie between the semiconductor and a larger printed circuit board. The function of the interposers is to serve as a “fan out” for the very high-density electrical outputs from the semiconductor. The interposer transitions the very high density electrical output from the semiconductor into a less dense output that is suitable for mounting an assembled packaging substrate (i.e., semiconductor package and semiconductor die) to the printed circuit board.
Today three major trends influence the electronics industry: an ever-increasing number of outputs from the semiconductor, miniaturization of all electronic components (especially semiconductor die and packaging substrates), and portability. As a result, these trends are forcing semiconductor packages to become smaller, which in turn requires circuit lines to become smaller, spaces between the circuit lines to become closer, and via holes connecting one side of the semiconductor package to the other to become smaller.
Depending on the number of output connections from the die, the final package size actually becomes larger because the routing of circuitry forces the semiconductor package to become denser. For instance, each input/output port (I/O) on the semiconductor die has to be connected to a circuit net on the wire bond area of the semiconductor package. Each circuit net on the semiconductor package is routed to a via hole to make the connection with the backside (ball attach side of the package). The ball attach area is attached to the printed circuit board. Thus, as circuit density increases, a limiting factor in package design is the size of the via hole and the size of the pad that surrounds the via hole. The area of the finished package is directly proportional to the number of I/Os on the semiconductor die and directly proportional to the area occupied on the printed circuit board. This high-density design makes it physically impossible to include an additional bus line for the electrical connection during electro plating between two bond fingers.
Due to the high-density design, semiconductor packages are generally manufactured by using a full body gold (FBG) process whereas, nickel and gold layers are the etch resist in the subsequent etching away of a copper layer. The circuitry is developed on both sides of the semiconductor package at the same time, resulting in the wire bond area having nickel and gold overhangs that expose the copper layer to the environment. As a result, the exposed copper can diffuse or oxidize, thus deteriorating the conductivity of the wire bond area. A gold layer is typically applied to both sides of the semiconductor package, and a solder mask is deposed directly onto the gold layer. However, solder mask-gold connections typically have poor adhesion. As can be seen, FBG manufacturing processes have several inherent weaknesses.
What is needed is a method for manufacturing semiconductor packages that overcomes the problems of FBG or other unreliable electrolysis processes.
SUMMARY OF THE INVENTION
The present invention is directed to high density, non-bussed semiconductor packages and a full body gold (FBG) method for manufacturing the semiconductor packages. According to an embodiment of the present invention, the semiconductor package is fabricated by developing circuitry on the wire bond side of the semiconductor package prior to developing the ball attach side. The copper circuitry on the wire bond side is fully covered by nickel and gold layers. Solder masks are applied directly to the substrate or copper layer to avoid contact with gold. In one embodiment of the present invention, nickel and gold layers cover the ball attach area. In another embodiment, the ball attach area is protected by an organic solderable material.
An advantage of the present invention is the fabrication of a semiconductor device that eliminates solder mask-gold connections. Since the presence of gold tend to weaken solder joints, avoiding such connections strengthens the electrical and mechanical connections to the semiconductor package.
Another advantage of the present invention is having a fully encapsulated wire bond area. Since the copper circuitry is fully covered by one or more layer of other material, it is protected from the environment, which reduces diffusion and oxidation.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.


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