Serial media independent interface

Details Serial media independent interface Serial media independent interface

1998-06-02

2002-05-07

Hsu, Alpus H. (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S401000, C370S402000

Reexamination Certificate

active

06385208

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to network computing. More specifically, the present invention relates to methods and apparatuses for connecting a system chip to a 10/100Base-T transceiver, and in particular, to a reduced pin-count serial media independent interface.
In computer network systems there is typically a natural division between chips handling the physical layer, which is responsible for transmitting data on the network, and the system chips, which perform logical operations with data transmitted on the network. Ethernet hubs, routers and switches are composed of multiple ports, and may be generically referred to as multi-port Ethernet devices. Each port is typically composed of a system chip, which includes a media access controller (“MAC”) layer, and a physical layer or “PHY.” Modern multi-port Ethernet devices typically integrate multiple MACs into one system chip (MAC chip) as well as multiple PHYs into another chip (PHY chip). An interface is required on each chip to transfer signals between the MACs and the PHYs.
IEEE standard 802.3u defines a media independent interface between a MAC layer and a PHY that includes 16 pins used for data and control. As noted above, in devices that include multiple ports that each have a MAC and a PHY, it is common to implement multiple MACs on one chip and multiple PHYs on another chip. If the standard MII, which includes 16 pins for data and control, is used for each MAC and PHY on the MAC chip and the PHY chip, the number of pins required for each chip becomes very large as multiple MACs and PHYs are included on single chips.
For example, typical switches available today may offer 24 ports in a single device. If all of the MACs were to be implemented on one chip and all of the PHYs were to be implemented on another chip then 384 pins would be required just to provide the interface between the MACs and the PHYs of the two chips. Obviously this is impractical. Thus, the requirement of 16 pins for data and control in the standard MII specification adds to the expense of MAC and PHY interfaces both by increasing the number of pins required on chips and by reducing the number of MACs and PHYs which may be combined on a single chip.
FIG. 1A
is a block diagram illustrating a standard MAC to PHY interface. A MAC
100
is connected to a PHY
102
via a 16 wire MII. PHY
102
is connected to a physical medium that transmits data over a network
104
. MAC
100
is connected to a network device
106
in a device that is using the MAC and the PHY to communicate. The device may be a switch, a repeater, a hub or any other network device that includes ports for communication using the Ethernet 802.3u standard.
FIG. 1B
is a block diagram illustrating the problem caused by the number of pins required in the standard MII MAC to PHY interface. A MAC chip
110
includes four MACs
112
a
,
112
b
,
112
c
, and
112
d
. Each of the four MACs must have 16 pins on the outside of the chip so that it can communicate with a PHY according to the MII standard. Similarly, a PHY chip
120
includes four PHYs
122
a
,
122
b
,
122
c
,
122
d
. Each of the PHYs must have 16 pins on the outside of the PHY chip so that it may communicate with the MAC via a standard 16 pin MII. Each PHY chip is also connected to a physical medium that is used to communicate over a network
130
.
It would be extremely useful if an alternative standard to the MII standard could be developed which would allow for communication between a MAC and a PHY using a reduced number of lines between the MAC and the PHY. This would reduce the number of pins per MAC or PHY included on a chip, reduce the cost of the chip, and allow more MACs or PHYs to be included on a single chip. An alternative interface to the MII should include all of the control signals and the same data capacity as the MII so that such an interface could continue to be interoperable with all systems that are intended to operate with an MII as described in IEEE standard 802.3u.
FIG. 2
is a block diagram illustrating the functions of the sixteen lines specified in the MII standard. A MAC
200
is connected to a PHY
202
using the 16 wire MII standard interface. The interface includes a transmit clock line
210
that provides a clock signal for clocking the transmitted data. A transmit enable line
212
indicates when data is being transmitted on the transmit data lines. A transmit error line
214
indicates an error should be forced onto the network. This line is used, for example, by repeaters to propagate errors that have been detected. A set of four lines
215
are used to transmit data. Since the overall data transfer rate between the MAC and the PHY is 100 MHz in a 100 Base-T system, each of the four data wires transmits at 25 MHz.
The MII also includes a carrier sense line
215
which indicates that data is being either received or transmitted. In addition, a collision line
220
is included which indicates that a collision has been detected, i. e., data is being both received and transmitted simultaneously. A receive clock line
222
is used to provide a clock for clocking the received data. A set of four receive data lines
224
each transfer data at 25 Mhz for an overall data rate of 100 MHz. A receive data valid line
226
indicates that valid data is being transferred on the receive data lines. A receive error line
228
indicates when an error has been detected in the received data, such as when an illegal symbol is detected by the PHY.
An MII is commonly used with a 100Base-TX PHY, for example, where data is transmitted across the physical medium of the network from PHY to PHY at a data rate of 125 MHz. Bits of data are grouped into individual symbols which include five bits each. The PHY receives each five bit symbol and translates it into a four bit nibble of data. Thus, the five bit symbol is used to transmit only four bits of data, with the remaining possible information states of the symbol used for error detection or other purposes. When errors are detected by the PHY, they are propagated to the MAC using the receive error line. Certain devices, such as repeaters, may use the transmit error line to propagate errors to other devices on a network. It should be noted that the receive data valid line differs from the carrier sense line in that the receive data valid line does not go high as soon as data begins to be received. Instead, the receive data valid line goes high after an entire five bit symbol corresponding to a nibble of valid data has been received and decoded, and remains high after data has stopped being received between PHYs to allow decoding of all four bits of the nibble corresponding to the last symbol transmitted. MIIs may also be used to connect a MAC to a PHY which uses another data transfer format, such as a 100Base-T4 PHY.
One approach to reducing the number of pins required for the MAC to PHY interface has been proposed by the Reduced Media Independent Interface™ (RMII™) consortium. The RMII provides a six pin interface between a MAC and a PHY. In addition to the six wires required for each MAC to PHY interface, a single synchronous clock signal is provided for both transmit data sent from the MAC to the PHY and the receive data sent from the PHY to the MAC. In the six pin RMII, two pins are used to transmit data and two pins are used to receive data. Each of the data transmit and the data receive lines runs at 50 Mhz. This provides a total bandwidth of 100 MHz for sending and a 100 MHz for receiving data across the MAC to PHY interface.
Thus, the RMII reduces the number of pins required to transmit and receive data from eight to four by doubling the clock speed of the data lines. The RMII reduces the eight pins required to send the remaining six control signals to only two pins by combining certain control signals and deriving other control signals in the manner described below. The transmit clock and the receive clock lines are eliminated for each individual MAC to PHY interface because a single synchronous clock is used for all of the inter

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