Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-07-18
2002-01-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S206000, C365S189050
Reexamination Certificate
active
06335902
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device comprising generating means for generating an internal clock signal for special mode, in particular, a semiconductor memory device such as a clock asynchronous DRAM (Dynamic Random Access Memory) for generating an internal clock signal for a special mode other than a normal mode.
2. Description of the Related Art
FIG. 17
is a block diagram showing a configuration of a clock asynchronous DRAM
100
of the related art.
Referring to
FIG. 17
, the DRAM
100
comprises the following interface terminals with external circuits, exclusive of a power supply terminal and a ground terminal:
(a) a clock input terminal T
1
for in putting an external clock signal for controlling each operation;
(b) an address input terminal T
2
for inputting an address signal for addressing memory cell arrays
20
-
1
,
20
-
2
,
20
-
3
and
20
-
4
; and
(c) a data input and output terminal T
3
for reading a data signal from the memory cell arrays
20
-
1
to
20
-
4
or writing data on the memory cell arrays
20
-
1
to
20
-
4
.
Such external clock signals and external signals such as an the address signal, the data signal and the like are inputted to an internal circuit of the DRAM
100
through buffer amplifiers
2
,
4
,
5
and
6
and a clock generator
3
.
First of all, the data signal is inputted to the data-in buffer amplifier
5
. The data-in buffer amplifier
5
converts the data signal having a predetermined external signal level into the data signal having a predetermined internal signal level (having the same high level as the level of an operating power supply voltage supplied to the DRAM, namely, the so-called CMOS level). Then, the data-in buffer amplifier
5
writes the data signal having the internal signal level in the memory cell arrays
20
-
1
to
20
-
4
through sense refresh amplifiers and input and output controllers
23
-
1
,
23
-
2
,
23
-
3
and
23
-
4
. On the other hand, the data signal, which is read out from the memory cell arrays
20
-
1
to
20
-
4
through the sense refresh amplifiers and input and output controllers
23
-
1
to
23
-
4
, is inputted to the data-out buffer amplifier
6
. The data-out buffer amplifier
6
converts the internal signal level of the data signal into the external signal level. Then, the data-out buffer amplifier
6
outputs the data signal having the external signal level through the data input and output terminal T
3
.
Moreover, the address signal is inputted to row decoders
21
-
1
to
21
-
4
and column decoders
22
-
1
to
22
-
4
through the address buffer amplifier
4
. The row decoders
21
-
1
to
21
-
4
and the column decoders
22
-
1
to
22
-
4
decode the input address signal, respectively, and then, specify specific addresses on the memory cell arrays
20
-
1
to
20
-
4
by using the decoded addresses.
Furthermore, the external clock signal is inputted to the clock buffer amplifier
2
in a control clock signal generating circuit
1
. The control clock signal generating circuit
1
comprises the clock buffer amplifier
2
and the clock generator
3
. The clock buffer amplifier
2
converts the input external clock signal into a reference clock signal, and then, outputs the reference clock signal to the clock generator
3
. The clock generator
3
converts the input reference clock signal into various types of control clock signals. Then, the clock generator
3
uses the control clock signals to execute a predetermined control process of the row decoders
21
-
1
to
21
-
4
, the column decoders
22
-
1
to
22
-
4
, the sense refresh amplifiers and input and output controllers
23
-
1
to
23
-
4
and an internal test controller (not shown).
FIG. 18
is a block diagram of a detailed configuration of the control clock signal generating circuit
1
of FIG.
17
.
Referring to
FIG. 18
, the external clock signals include an external {overscore (RAS)} signal, an external {overscore (CAS)} signal, an external {overscore (WE)} signal and an external {overscore (OE)} signal. In the specification and drawings, an upper line of each signal indicates a low enable signal for activating the operation at low level. The {overscore (RAS)} signal is a row address control signal for controlling the latch of a row address, the amplification of data from the memory cell arrays, a refresh operation and an active or precharge operation of the overall DRAM chip. Moreover, the {overscore (CAS)} signal is a column address control signal for controlling the latch of a column address, a read operation of data from the memory cell arrays or a write operation of data in the memory cell arrays. Furthermore, the {overscore (WE)} signal is a write enable signal for controlling the read operation of data from the memory cell arrays or the write operation of data in the memory cell arrays. Furthermore, the {overscore (OE)} signal is an output enable signal for controlling the read operation of data from the memory cell arrays.
The external {overscore (RAS)} signal is inputted to an input buffer amplifier
7
-
1
. The input buffer amplifier
7
-
1
converts the external {overscore (RAS)} signal having the external signal level into an internal {overscore (RAS)} signal having the internal signal level, and then, outputs the internal {overscore (RAS)} signal to the clock buffer amplifier
2
. Moreover, the external {overscore (CAS)} signal is inputted to an input buffer amplifier
7
-
2
. The input buffer amplifier
7
-
2
converts the external {overscore (CAS)} signal having the external signal level into an internal {overscore (CAS)} signal having the internal signal level, and then, outputs the internal {overscore (CAS)} signal to the clock buffer amplifier
2
. Furthermore, the external {overscore (WE)} signal is inputted to an input buffer amplifier
7
-
3
. The input buffer amplifier
7
-
3
converts the external {overscore (WE)} signal having the external signal level into an internal {overscore (WE)} signal having the internal signal level, and then, outputs the internal {overscore (WE)} signal to the clock buffer amplifier
2
. Furthermore, the external {overscore (OE)} signal is inputted to an input buffer amplifier
7
-
4
. The input buffer amplifier
7
-
4
converts the external {overscore (OE)} signal having the external signal level into an internal {overscore (OE)} signal having the internal signal level, and then, outputs the internal {overscore (OE)} signal to the clock buffer amplifier
2
. Therefore, internal clock signals include the internal {overscore (RAS)} signal, the internal {overscore (CAS)} signal, the internal {overscore (WE)} signal and the internal {overscore (OE)} signal.
The clock buffer amplifier
2
and the clock generator
3
constitute a control clock generator
30
. The clock buffer amplifier
2
generates a predetermined plurality of reference clock signals in accordance with the internal {overscore (RAS)} signal, the internal {overscore (CAS)} signal, the internal {overscore (WE)} signal and the internal {overscore (OE)} signal, and then, outputs the reference clock signals to the clock generator
3
. The clock generator
3
generates and outputs the control clock signal in accordance with the input reference clock signals. The control clock signals include the row address control signal, the column address control signal, a write and read control signal, a refresh mode control signal and a test mode control signal, as shown in FIG.
18
.
FIG. 19
is a circuit diagram showing a configuration of a control clock generator
30
a
for a normal mode, which is an example of the control clock generator
30
of FIG.
18
. Referring to
FIG. 19
, the control clock generator
30
a
comprises two inverters INV
1
and INV
2
, a NAND gate NAND
1
and an AND gate AND
1
with an inverted input terminal. The control clock generator
30
a
generates a {overscore (RASE)} signal for controlling a row system control circuit
24
in accordance with the internal {overscore (RAS)} signal and reference clock signals &phgr;
1
and
Elms Richard
McDermott & Will & Emery
Nguyen Tuan T.
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