Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond
Reexamination Certificate
1998-12-29
2002-09-03
Lam, Cathy (Department: 1775)
Stock material or miscellaneous articles
Structurally defined web or sheet
Discontinuous or differential coating, impregnation or bond
C257S774000, C257S784000, C257S786000
Reexamination Certificate
active
06444295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for improving integrated circuits bonding firmness and, more particularly, to regular or irregular layout patterns formed under bond pads.
2. Description of the Prior Art
As the increment of integration, the multi-level interconnection must be used for the coupling of internal circuits during the fabrication of semiconductor devices because that the single metal connect is not sufficient for using. In general, many semiconductor devices utilize bond pads and bond wires to form the electrically coupling between internal and external circuits. Because the bond pads are formed on the upper metal layer of the multi-level interconnection, the upper metal layer of the multi-level interconnection are usually called as “bond pad metal layer”. The formation of bond pads includes photolithography and etching processes to form bond pad windows in the passivation layer, which covers the devices formed previously, and then expose the predetermined areas located in the “bond pad metal layer”. After the bond pad windows are formed, thin wires are bonded into the bond pad windows to couple with the predetermined areas served as bond pads.
The bond wires are tensioned and sheared during the devices are packaged, which may cause the peeling of bond wires and thus bring about the failure of the devices. There are many prior arts to solve the foregoing problem. For example, the U.S. Pat. No. 5,695,592 (Dec. 9, 1997) entitled “Method of adhesively bonding mineral particles to support” or the U.S. Pat. No. 5,700,581 (Dec. 23, 1997) entitled “Solvent-free epoxy based adhesives for semiconductor chip attachment”. Another method is to modify the structure of bond pads for increasing firmness of bond wire. For example, the U.S. Pat. No. 5,686,762 (Nov. 11, 1997) titled “Semiconductor device with improved bond pads”. Among these methods, the U.S. Pat. No. 5,686,762 is described accompanied with the FIG.
1
. At least one opening is formed in the bonding surface of bond pads and the opening(s)
22
may recesses extending partially into the bonding surface or channels that extend entirely through the bond pad. This method increases the firmness of bond wire efficiently but additional steps are needed during the forming of opening(s)
22
. Such as an additional photomask of the opening(s)
22
pattern—additional photolithography process—removal of the photoresistor and etching processes process and so on. In
FIG. 1
, the object
12
is an internal circuit; the object
16
is the bond pad window the object
18
is a passivation layer and the object
20
is an insulator layer.
The method disclosed in the present invention is easier than aforesaid methods, because additional steps or cost is not necessary for the present invention. The feature of the present invention is to make the bonding surface of metal layer under and most close to the bond pad layer (the top metal layer of multi-level interconnection) rough, which leads to improving the firmness of bond wire. The principle of roughness process is, under the predetermined regions serve as bond pads, to form a metal layer with regular or irregular layout patterns. It's worthy to note that the roughness process is be implemented in the meanwhile of the deposition of the metal layer under the bond pad layer. In other words, it doesn't require additional steps or cost because the photomasks of layout pattern and that of metal layer are the same one.
SUMMARY OF THE INVENTION
During the devices are packaged, the break of bond wires or the peeling of bond pads occurs frequently and thus result in the failure of the devices. In order to improve the firmness of bond wires, the present invention discloses a method, which makes the metal layer under and most close to the bond pad metal layer (the upper metal layer of multi-level interconnection)rough. The method of making rough is, under the bond pad metal, to form a metal layer with regular or irregular layout patterns to result in the undulation of upper surface. The bonding surface of later bond pads formed on the metal is affected by the undulation, and thus improves the firmness of bond wires.
The preferred embodiment of the present invention is described as follow An internal circuit is formed on a substrate by conventional method. This internal circuit comprises several metal-oxide semiconductors (MOSs) or other semiconductor devices. An insulator layer is formed on the internal circuit and then several contact holes are formed in the insulator layer by photolithography and etching processes. Several plugs are formed in the contact holes and couple to the internal circuit. A composition layer is formed, which serves as a part of the multi-level interconnection. The composition layer is composed with at least one metal layer and at least one inter-metal dielectric layer (IMD), and each film of the composition layer is piled on top of each other. The bottom and the top of the composition layer are a metal layer and a dielectric layer, respectively. There are several vias and several via plugs in each inter-metal dielectric layer, and these via plugs serve to make the metal layers coupling to the internal circuit. It's worthy to note that, under the specific regions serving as bond pads, the top metal layer of the composition layer has a regular or an irregular layout pattern.
The method disclosed in the present invention is applied in multi-level interconnection. If the number of metal layers of the multi-level interconnection are 3, the number of metal layers of the composition layer are 2; the inter-metal dielectric layers (IMD) of the composition layer serve as isolation and whose number are 2, too.
A bond pad layer is formed on the composition layer. Then a passivation layer is formed on the bond pad layer. The passivation layer serves to protect the internal circuit from moisture and alkali ions. Then by photolithography and etching processes; bond pad windows are formed in the passivation layer to expose the bond pad layer. Finally, the bond wires are bonded to the bond pads.
After the aforesaid steps are finished, a test machine was used to test the firmness of the bond wires. The test result reveals that no matter whether ball shear test or wire pull test, the bond pads using present invention satisfy the industrial standard (wire pull is 5 mg and ball shear is 30 mg)
REFERENCES:
patent: 5045919 (1991-09-01), Nagaoka
patent: 5430329 (1995-07-01), Harada et al.
patent: 5686762 (1997-11-01), Langley
patent: 5695592 (1997-12-01), Rouaud et al.
patent: 5707894 (1998-01-01), Hsiao
patent: 5753975 (1998-05-01), Matsuno
patent: 5874779 (1999-02-01), Matsuno
Ker Ming-Dou
Peng Jeng-Jie
Wang Nien-Ming
Industrial Technology Research Institute
Lam Cathy
LandOfFree
Method for improving integrated circuits bonding firmness does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving integrated circuits bonding firmness, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving integrated circuits bonding firmness will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2851095