Semiconductor memory with multistage local sense amplifier

Details Semiconductor memory with multistage local sense amplifier Semiconductor memory with multistage local sense amplifier

2000-09-14

2002-07-23

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230030, C365S205000

Reexamination Certificate

active

06424554

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor memory device such as SRAM and in particular to a structure of a sense amplifier which amplifies data on bit lines of the semiconductor memory device.
2. Description of Related Art
FIG. 1
shows a circuit diagram of SRAM according to a related art. Each memory cell (cell) is connected to a paired bit line BL and EL (/BL or BLbar). These arrayed memory cells are called memory cell array. In this related art, there are eight paired bit lines (BL<
0
> and /BL<
0
> to BL<
7
> and /BL<
7
>), and each bit line is connected to a PMOS transistor T as a transfer gate. Each bit line is connected to a local sense amplifier
1
via the PMOS transistor T.
The circuit of
FIG. 1
requires a plurality of local sense amplifiers
1
since these memory cells are arranged horizontally. The plurality of local sense amplifiers
1
is connected to a data bus
2
for outputting data stored in these cells.
The data bus
2
is connected to a global sense amplifier
3
connected an output buffer
4
. The global sense amplifier
3
is generally arranged close to the output buffer
4
.
The each memory cell (cell) is connected to a word line
5
, and the each PMOS transistor T are connected to a control line
6
.
The method of outputting data from this SRAM is explained below. Data stored in a memory cell connected to word line
5
selected according to row address are transferred to the bit line (for example BL<
0
> and /BL<
0
> of FIG.
1
). And then, only the data in the bit line selected based on column address on the control line
6
is inputted to the local sense amplifier
1
via transfer gate T (for example, the first and second PMOS transistor from the left of the FIG.
1
). The output data of the local sense amplifier
1
is outputted to the global sense amplifier
3
via the data bus
2
. The global sense amplifier
3
amplifies the output data to output to the output buffer
4
. The output buffer
4
may output the data to outside of this device.
In this semiconductor memory device of the related art, the static capacitance of data bus
2
increases very much in order to connect a large number of local sense amplifiers
1
(for example, sixty four (64)) to the data bus
2
. Therefore, when the local sense amplifier
1
senses the data, it needs to charge a large static capacitance. Then, larger power is required in case of shorten senses time is required. Namely, there is a problem that the sense time is lengthened in case of less power supply to the local sense amplifier
1
.
Here, it is possible to shorten the charging time of the static capacitance of the outputting data, if the power of local sense amplifier
1
is further increased. In general, however, the upper limit of electric power in the LSI chip is often predetermined. Therefore, there is a limit in increasing power of local sense amplifier
1
for faster outputting.
SUMMARY OF THE INVENTION
Accordingly, present invention is to provide a novel semiconductor memory device capable of improving sense time for high-speed data outputting, while increasing power at the sensing is restrained.
A semiconductor memory of the present invention comprises a plurality of paired bit lines; a plurality of memory cells; a plurality of first local sense amplifiers connected to at least one bit line of the paired bit lines, for amplifying data output from the bit lines; a plurality of second local sense amplifiers connected to the first local amplifiers, for amplifying data output from the first local sense amplifiers; and a data bus connected to the second local sense amplifiers, for transferring data output from the second local sense amplifiers.


REFERENCES:
patent: 5585747 (1996-12-01), Proebsting
patent: 5696726 (1997-12-01), Tsukikawa
patent: 5719815 (1998-02-01), Takahashi et al.
patent: 5991223 (1999-11-01), Kozaru et al.

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