Drive apparatus and method of light emission element array

Details Drive apparatus and method of light emission element array Drive apparatus and method of light emission element array

1998-12-22

2002-05-21

Hjerpe, Richard (Department: 2774)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S061000, C345S039000, C345S044000, C345S083000, C345S076000, C345S183000, C257S088000, C257S113000, C340S457100

Reexamination Certificate

active

06392615

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to light emission element array drive apparatus and method for sequentially setting at least one or more light emission thyristor groups arranged in array, into a lighting state.
2. Related Background Art
Conventionally, a self-scanning type light emission element array (SLED) has been disclosed in Japanese Patent Application Laid-Open Nos. 1-238962, 2-208067, 2-212170, 3-20457, 3-194978, 4-5872, 4-23367, 4-296579 and 5-84971; “Proposal of Light Emission Element Array For Optical Printer Integrating Drive Circuits” JAPAN HARD COPY, 1991 (A-17); “Proposal Of Self-Scanning Type Light Emission Element (SLED) Using PNPN Thyristor Structure” THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, Mar. 5, 1991; and the like. Such the SLED has been widely noticed as a recording light emission element.
FIG. 1
shows an example of a SLED
100
as a light emission element array. In the conventional art,
FIG. 2
is a timing chart of various control signals externally transmitted to the SLED
100
to control the SLED
100
shown in
FIG. 1
, and indicates an example of a case where all the light emission elements are driven.
In
FIG. 1
, a VGA
101
corresponding to a power supply voltage of the SLED
100
is connected to diodes
141
,
142
,
143
,
144
and
145
. These diodes
141
,
142
,
143
,
144
and
145
are cascade connected to a start pulse &phgr;S
145
respectively through resistors
102
,
103
,
104
,
105
and
106
. As shown in
FIG. 1
, the SLED
100
is composed of a group in which shift thyristors S
1
′, S
2
′, S
3
′, S
4
′ and S
5
′ are arranged in array as control elements, a group in which light emission thyristors S
1
, S
2
, S
3
, S
4
and S
5
are arranged in array as light emission elements, and the like. Gate signals of the light emission thyristors and the shift thyristors are connected to each other. For example, the gate signal of the first light emission thyristor S
1
is connected to the gate signal of the first shift thyristor S
1
′, and further connected to a signal input section Va to which the start pulse &phgr;S
145
is transmitted. The gate signal of the second light emission thyristor S
2
is connected to the gate signal of the second shift thyristor S
2
′, and further connected to a cathode Vb of the diode
141
which is connected to the terminal Va to which the start pulse &phgr;S
145
is transmitted. The gate signal of the third light emission thyristor S
3
is connected to the gate signal of the third shift thyristor S
3
′, and further connected to a cathode Vc of the diode
142
. Similarly, the gate signal of the fifth light emission thyristor S
5
is connected to the gate signal of the fifth shift thyristor S
5
′, and further connected to a cathode Ve of the diode
144
.
Hereinafter, a driving method of the SLED
100
will be described with reference to the timing chart shown in FIG.
2
.
In
FIG. 2
, initially, voltage of the start pulse &phgr;S
145
is varied from 0V to 5V. By varying the voltage of the start pulse &phgr;S
145
to 5V, a voltage of the Va becomes 5.0V, a voltage of the Vb becomes 3.6V (forward direction voltage down is 1.4V), a voltage of the Vc becomes 2.2V, a voltage of the Vd becomes 0.8V, voltages of the Ve and the following become 0. V. Then, voltage of the gate signals of the shift thyristors S
1
′ and S
2
′ are varied from 0V to 5.0V and 3.6V respectively. In this state, by varying voltage of a shift pulse &phgr;
1
135
from 5V to 0V, potentials of anode, cathode and gate of the shift thyristor S
1
′ become 5V, 0V and 3.6V respectively. Thus, the thyristor becomes an ON condition, whereby the shift thyristor S
1
′ becomes an ON state. In this state, even if the voltage of the start pulse &phgr;S
145
is set at 0V, since the shift thyristor S
1
′ is in the ON state, the voltage of the Va becomes 5V (e.g., 4.8V in FIG.
2
). This is because the pulse is applied through the resistor
102
, concerning the start pulse &phgr;S
145
, and the potential difference between the anode and gate becomes almost zero upon setting the thyristor into an ON state. Therefore, even if the voltage of the start pulse &phgr;S
145
is set at 0V, the ON state of the first shift thyristor S
1
′ is maintained and a first shifting operation terminates. In this state, if voltage of a light emission thyristor drive clock &phgr;I
110
is varied from 5V to 0V, since the light emission thyristor S
1
comes to have the same condition as that in which the shift thyristor S
1
′ becomes the ON state, the light emission thyristor S
1
becomes an ON state and the first light emission thyristor S
1
is lighted. At the first light emission thyristor S
1
, the potential difference between an anode and a cathode of the light emission thyristor S
1
becomes zero by returning the voltage of the light emission thyristor drive clock &phgr;I
110
to 5V. Thus, since a minimum maintaining current for the light emission thyristor S
1
can not be flowed, the light emission thyristor S
1
becomes an OFF state, thereby lighting off the thyristor S
1
.
Subsequently, transfer of the ON state of the thyristor from the shift thyristor S
1
′ to the shift thyristor S
2
′ will be explained. Even if the light emission thyristor S
1
becomes the OFF state, the voltage of the shift pulse &phgr;
1
135
is still 0V. Thus, also the shift thyristor S
1
′ is still in the ON state, the gate voltage Va of the shift thyristor S
1
′ is 5V (e.g., 4.8V in
FIG. 2
) and the voltage of the Vb is 3.6V. In this state, by varying voltage of a shift pulse &phgr;
2
120
from 5V to 0V, anode, cathode and gate voltages of the shift thyristor S
2
′ become 5V, 0V and 3.6V respectively, whereby the shift thyristor S
2
′ becomes an ON state. After the shift thyristor S
2
′ becomes the ON state, by varying the voltage of the shift pulse &phgr;
1
135
from 0V to 5V, the shift thyristor S
1
′ becomes an OFF state in the manner similar to that the light emission thyristor S
1
became the OFF state. Thus, the ON state of the shift thyristor is transferred from the shift thyristor S
1
′ to the shift thyristor S
2
′. Then, the light emission thyristor S
2
can be selectively lighted by varying the voltage of the light emission thyristor drive clock &phgr;I
110
from 5V to 0V. Hereinafter, the reason of lighting only the light emission thyristor of which corresponding shift thyristor is in the ON state will be explained. Since gate voltages of thyristors other than the both-side thyristors (e.g., S
1
′ and S
3
′) of the ON state thyristor (e.g., S
2
′) are 0V, the thyristors do not become the ON state. Also, as to the both-side shift thyristors (e.g., S
1
′ and S
3
′), since potential of the drive clock &phgr;I
110
becomes 3.6V (forward direction voltage down at each light emission thyristor) due to the fact that the shift thyristor (e.g., S
2
′) becomes the ON state, the both-side thyristors (e.g., S
1
′ and S
3
′) become such a state as the potential difference between the gate and the cathode is minimized and a minimum maintaining current for the thyristors can not be flowed. Therefore, it is impossible to set the both-side shift thyristors (e.g., S
1
′ and S
3
′) into an ON state.
As described above, conventionally, when the voltage 5V of the start pulse &phgr;S
145
is supplied, the first bit shift thyristor S
1
′ is set into an ON state by varying the voltage of the shift pulse &phgr;
1
135
(acting as drive signal for odd-number shift thyristors S
1
′ and S
3
′) to 0V, and the gate voltage of the light emission thyristor S
1
is maintained at 5V. Thereafter, the voltage of the light emission thyristor drive clock &phgr;I
110
for the light emission thyristor S
1
is set at 0V, thereby lighting the light emission thyristor S
1
.
However, shift speed of sequentiall

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