ESD protection in mixed signal ICs

Details ESD protection in mixed signal ICs ESD protection in mixed signal ICs

2000-04-07

2002-09-24

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06456472

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to circuits for electrostatic discharge (ESD) protection and more particularly to such circuits which provide better isolation between power supplies.
BACKGROUND TO THE INVENTION
Electrostatic discharge (ESD) is a problem for most integrated circuits (ICs). If not properly diffused, ESD can damage, destroy, or render unreliable an IC. Protection circuits must therefore be incorporated into ICs so that ESD current can be safely diffused. ESD current can be in the order of amperes with a duration lasting anywhere from 1 ns to 100 ns. These ESD protection circuits must therefore be able to handle such large currents.
In order to provide ESD protection, there must be a low impedance electrical circuit between any two pins on the IC. This circuit must be able to tolerate the range of ESD current values, usually in the order of 1 AMP, while simultaneously not developing a voltage too large for the device. As an example, in a 0.5 &mgr;m CMOS process, the maximum voltage across any one transistor may be 3.6 volts.
In mixed signal ICs, ICs which handle both analog and digital signals, another main concern is interference between these two types of signals. This problem has been partially solved by separating the power supplies for the analog and digital portions of the IC.
Previously, one solution to theses two problems was the use of a single clamping circuit connected to the different power supply pads. Worley et al. in U.S. Pat. No. 5,654,862 uses a single clamp connected to a bus which is in turn connected to the separate power supply pads. Unfortunately, this solution has run into problems in applications where isolation between supplies is critical. Capacitance effects due to the coupling diodes do not provide sufficient isolation between power supplies. Interference between analog and digital signals therefore occur, rendering this solution ineffective for applications where isolation is critical.
Referring to
FIG. 1
, a schematic diagram of a prior art ESD protection circuit is illustrated. A first pair of diodes
10
,
20
are serially coupled at junction
30
. At a first end
40
of the pair of diodes
10
,
20
, a V
DD
power supply pad
50
is connected. At the second end
60
of the pair of diodes
10
,
20
, a V
ss
local ground
70
is connected. An input/output (I/O) pad
80
is coupled to the pair of diodes
10
,
20
at junction
30
. Coupled in parallel across the pair of diodes
10
,
20
, is a clamp circuit, in this case a Zener diode
90
.
The pair of diodes
10
,
20
, allow current to flow in the direction indicated by arrow A. When the voltage between ends
40
,
60
reach a certain value, the Zener diode
90
's breakdown voltage, current flows through the Zener diode
90
in the direction of arrow B. This provides a path between any two of the pads
50
,
80
70
, thereby allowing any ESD current to be dissipated through the local ground
70
. Also, the Zener diode
90
, in breakdown mode, clamps the voltage between ends
40
,
60
to a specific value, thereby preventing possible over voltage conditions.
However, the circuit of
FIG. 1
still does not provide enough isolation between power supplies in mixed signal ICs.
What is therefore needed is a circuit which provides maximum isolation between the analog and the digital signals while providing ESD protection.
SUMMARY OF THE INVENTION
The invention provides ESD protection for IC's while isolating the different power supplies from one another. A network in the IC has a plurality of circuit cells through which the IC receives power. Each circuit cell also provides localized electrostatic discharge protection. With each circuit cell coupled to a global node through a dual current direction coupling network and with portions of the global node physically separating the circuit cells, any noise, interference, or stray ESD current generated by a circuit cell is shunted away from other circuit cells to the global node. An off-chip ground connection coupled to the global node provides a destination for this noise or interference.
In a first embodiment, the invention provides a network for electrostatic discharge protection in an integrated circuit, the network comprising:
a global node coupled to an off-chip ground connection;
a plurality of circuit cells, each cell comprising:
a first pair of serially coupled diodes, said first pair allowing current to flow in a first direction;
a positive power supply pad coupled to a first end of the first pair of diodes;
a negative power supply pad coupled to a second end of the first pair of diodes;
an I/O pad coupled to a junction point between the first pair of diodes;
a circuit clamp connected in parallel with said first pair of diodes, said clamp being connected between the first end of the first pair of diodes and the second end of the first pair of diodes, said clamp providing a path for current to flow in a second direction;
a coupling network coupled between an end of the first pair of diodes and the global node
wherein
the first direction is opposite the second direction, and
the coupling network allows current to flow in two opposing directions.
In a second embodiment, the invention provides a network for electrostatic discharge protection in an integrated circuit, the network comprising:
a global node;
a plurality of circuit cells, each circuit cell having a plurality of power supply pads and each circuit cell providing local electrostatic discharge protection within the cell;
a plurality of coupling networks, each coupling network coupling a circuit cell to the global node; wherein
the coupling network allows current to flow in two opposing directions.


REFERENCES:
patent: 5515225 (1996-05-01), Gens et al.
patent: 5991135 (1999-11-01), Saleh
patent: 6078068 (2000-06-01), Tamura
patent: 6104588 (2000-08-01), Hariton et al.

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