Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-02-17
2002-09-03
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S718000, C257S721000, C257S747000
Reexamination Certificate
active
06445062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a cavity therein, such as a flip-chip type semiconductor device, and a method of fabricating the same.
2. Description of the Related Art
A semiconductor package comprised of a substrate composed of organic material and a semiconductor chip flip-chip-mounted on the substrate generally has a cavity inside thereof.
FIGS. 1A
to
1
C illustrate a conventional semiconductor device.
FIG. 1A
is a top view of the semiconductor device with a cover taken away,
FIG. 1B
is a cross-sectional view taken along the line IB—IB in
FIG. 1A
, and
FIG. 1C
is a cross-sectional view taken along the line IC—IC in FIG.
1
A.
The illustrated conventional semiconductor device is comprised of a square substrate
2
, a square semiconductor chip
4
mounted centrally on the substrate
2
, a wall
3
having a cross-section of a hollow square pole and mounted on edges of the substrate
2
so that the semiconductor chip
4
is surrounded by the wall
3
, a square cover
8
covering the wall
3
therewith, first adhesive
7
adhering the cover
8
to the wall
3
and also adhering the wall
3
to the substrate
2
, second adhesive
5
applied between the semiconductor chip
4
and a lower surface of the cover
8
for radiating heat therethrough, and a plurality of spherical solder balls
9
arranged on a lower surface of the substrate
2
.
The cover
8
has almost the same area as an area of the substrate
2
. The semiconductor chip
4
has a projected area smaller than an area of the cover
8
. The wall
3
has four sides each of which is equal in length to each of sides of the substrate
2
, and is coextensive with the substrate
2
.
The substrate
2
may be comprised of a film or may have a multi-layered structure composed of organic material. The wall
3
is composed of copper. The cover
8
is composed of a material having a high thermal conductivity, such as copper, aluminum, silicon carbide, and aluminum nitride. The first adhesive is composed of epoxy having a low coefficient of water absorption, cyanate ester, or polyolefin.
Pads (not illustrated) formed on the substrate
2
make contact with bumps (not illustrated) formed at a surface of the semiconductor chip
4
to thereby ensure electrical connection between the substrate
2
and the semiconductor chip
4
. The wall
3
is mounted on the substrate
2
in order to enhance mechanical strength of the semiconductor device. The wall
3
is adhered to the substrate
2
through the first adhesive
7
without a gap. The cover
8
is adhered to the wall
3
through the first adhesive
7
in an opposite side of the substrate
2
.
The second adhesive
5
is applied between an upper surface of the semiconductor chip
4
and a lower surface of the cover
8
to thereby hermetically adhere the semiconductor chip
4
to the cover
8
without any gap. The solder balls
9
are equally spaced from one another on a lower surface of the substrate
2
.
The conventional semiconductor device having the above-mentioned structure is accompanied with a problem that since there is a difference in a thermal expansion coefficient between silicon of which the semiconductor chip
4
is composed and organic material of which the substrate
2
is composed, the substrate
2
is deformed in an annealing step to be carried out after flip-chip mounting of the semiconductor chip
4
onto the substrate
2
, resulting in that solder connection is peeled off, or that the semiconductor chip
4
is peeled off the substrate
2
, as illustrated in
FIGS. 2A and 2B
.
In order to solve this problem, an attempt has been made to introduce underfilling resin between the semiconductor chip
4
and the substrate
2
, and then, cure the underfilling resin. This attempt ensures enhancement in strength around bumps, and provides resistance to deformation to the substrate
2
.
FIGS. 3A
to
3
G are cross-sectional views of a conventional semiconductor device in which a semiconductor chip is fixed on a substrate through underfilling resin. Hereinbelow is explained the method of fabricating such a semiconductor chip, with reference to
FIGS. 3A
to
3
G.
First, as illustrated in
FIG. 3A
, there is prepared the substrate
2
.
Then, as illustrated in
FIG. 3B
, the wall
3
having a cross-section of a hollow square pole is fixed on the substrate through the first adhesive
7
.
Then, as illustrated in
FIG. 3C
, the semiconductor chip
4
is electrically connected to the substrate
2
by causing pads (not illustrated) of the substrate
2
to make contact with bumps (not illustrated) of the semiconductor chip
4
. Then, a product resulting from the step illustrated in
FIG. 3C
is washed with flux.
Then, as illustrated in
FIG. 3D
, underfilling resin
6
is coated between the substrate
2
and the semiconductor chip
4
, and then, heated. As a result, the underfilling resin
6
is cured and thus adhered to both the substrate
2
and the semiconductor chip
4
.
Then, the second adhesive
5
for radiating heat therethrough is applied onto an upper surface of the semiconductor chip
4
. Then, the cover
8
is put on the wall
3
, as illustrated in FIG.
3
E. Since the first adhesive
7
is applied to a lower surface of the cover
8
at a peripheral area thereof, the cover
8
is adhered to the wall
3
. Then, the semiconductor device is heated. As a result, the first adhesive
7
is cured, and accordingly, the wall
3
is fixed to both the substrate
2
and the cover
8
.
Then, the semiconductor device is turned upside down, and thereafter, the solder balls
9
are adhered to a lower surface of the substrate
2
by means of a jig
11
. The solder balls
9
are vacuum-sucked to the jig
11
, and the solder balls
9
are mounted onto a lower surface of the substrate
2
at a time, as illustrated in FIG.
3
F.
Then, a product resulting from the step illustrated in
FIG. 3F
is washed with flux. Thus, the semiconductor device as illustrated in
FIG. 3G
is completed.
The semiconductor device illustrated in
FIG. 3G
has the same structure as the structure of the semiconductor device illustrated in
FIGS. 1A
to
1
C except addition of the underfilling resin
6
. The underfilling resin
6
is liquid resin containing epoxy, cyanate ester or polyolefin as a main constituent.
In the process of fabricating the semiconductor device illustrated in
FIGS. 3A
to
3
G, annealing steps are carried out twice, one for curing the underfilling resin
6
in the step illustrated in
FIG. 3D
, and the other for curing the second adhesive
7
in the step illustrated in FIG.
3
E. In addition, three annealing steps are carried out each for aging, baking and mounting the semiconductor device on a printed wiring board, after the semiconductor device has been completed. Those annealing steps are carried out at a temperature of about 125, 125 and 230 degrees centigrade, respectively.
Though the above-mentioned problem of deformation of the substrate
2
is caused even in the annealing steps to be carried out after the semiconductor device has been completed, the addition of the underfilling resin
6
can prevent occurrence of the problem.
However, after the underfilling resin
6
has been cured, the underfilling resin
6
contracts, causing another problem that the substrate
2
is made bent, and the semiconductor chip
4
is cracked.
Japanese Unexamined Patent Publication No. 11-204552 published on Jul. 30, 1999 has suggested a solution to this problem. Specifically, Japanese Unexamined Patent Publication No. 11-204552 has suggested a semiconductor device including an underfilling resin coated between a printed wiring board and a semiconductor chip, and adhesive partially coated onto the semiconductor chip for radiating heat therethrough. The underfilling resin and the adhesive are to be concurrently cured. As a result, even if stresses are generated due to contraction of the resin, those stresses are cancelled each other and relaxed, p
Chaudhuri Olik
Ha Nathan W.
Hutchins, Wheeler & Dittmar
NEC Corporation
LandOfFree
Semiconductor device having a flip chip cavity with lower... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a flip chip cavity with lower..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a flip chip cavity with lower... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2849305