Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-01-30
2002-09-17
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S685000, C257S686000, C257S784000
Reexamination Certificate
active
06452279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having stacked semiconductor chips mounted on a substrate.
2. Description of the Background Art
For convenience to users and scale reduction of semiconductor devices, a semiconductor device has been used in which two semiconductor chips are housed in one CSP (chip scale package). Referring to
FIGS. 4A and 4B
, in a conventional CSP, the first semiconductor chip
101
and the second semiconductor chip
102
are stacked with a shift so that one semiconductor chip may not cover the connection pads (not illustrated) disposed on the other semiconductor chip. This stack is fixed with an insulating adhesive layer
108
. The semiconductor chips
101
,
102
are connected to an input/output terminal
104
disposed on the front surface of a glass epoxy substrate
105
with the use of a gold wire
106
, and the whole is sealed with an epoxy resin
107
. A solder ball
109
is provided on the rear surface side of the glass epoxy substrate
105
, and the semiconductor device is connected to another device via this solder ball.
However, since the above-mentioned two semiconductor chips
101
,
102
are disposed in a shifted configuration so that one may not cover the connection pad of the other, there has been an inconvenience such that the arrangement of the connection pad particularly of the semiconductor chip disposed on the lowermost part is restricted. For example, in the case of a semiconductor device in which two semiconductor chips of 64 M-DRAM (dynamic random access memory) are mounted in a CSP, this inconvenience is conspicuous. In other words, although they are semiconductor chips having the same shape, the upper semiconductor chip must be shifted so as to avoid the connection pad disposed on the lower semiconductor chip (semiconductor chip placed on the lower side). For this reason, the scale reduction of the package is inhibited in a fundamental part.
Here, the terms “upper” and “lower” are used to mean that, in two semiconductor chips stacked on a substrate, the lower semiconductor chip is disposed nearer to the substrate and the upper semiconductor chip is disposed farther to the substrate. Further, a downward oriented semiconductor chip refers to a semiconductor chip whose connection pad faces the substrate, and the upward oriented semiconductor chip refers to a semiconductor chip whose connection pad faces away from the substrate.
High integration and scale reduction of semiconductor devices is constantly sought for, and a higher degree of integration and scale reduction is desired with a simple production process. In other words, it is always desired to develop, with a simple production process, a semiconductor device whose degree of scale reduction exceeds that of a previous semiconductor device even only a little.
Further, as noted before, in stacking semiconductor chips, it is desired that no restriction is imposed such as the arrangement in which one semiconductor chip does not cover the connection pad of the other semiconductor chip. In other words, it is desired to provide a convenient arrangement for improvement of frequency characteristics and electric characteristics and for scale reduction without the above-mentioned restriction.
SUMMARY OF THE INVENTION
The first object of the present invention is to provide a packaged semiconductor device having a high degree of integration with a more reduced scale. Further, the second object of the present invention is to avoid the restriction of the arrangement of the connection pads which is imposed for preventing the connection pads of one semiconductor device from being covered with the other semiconductor chip.
A semiconductor device according to the first aspect of the present invention has two or more semiconductor chips including first and second semiconductor chips stacked on a substrate, wherein a connection pad of the first semiconductor chip faces the substrate, and the first and second semiconductor chips are both connected to input/output terminals of the substrate by means of wires.
According to the above-mentioned construction, the downward oriented first semiconductor chip is wired in a BOC (board on chip) manner, and if the second semiconductor chip is upward oriented, the second semiconductor chip is wired in a FBGA (fine ball grid array) manner, thereby to be respectively connected to an input/output terminal of the substrate. In this construction, if the second semiconductor chip is upward oriented and stacked adjacent to the first semiconductor chip, the two semiconductor chips are in a back-to-back configuration, thereby eliminating the possibility that the connection pad of one semiconductor chip is covered (hidden) by the other semiconductor chip, so that there is no restriction imposed on the arrangement of the connection pads. Therefore, the arrangement of the connection pads can be designed taking the chip size, the frequency characteristics, and the electrical characteristics into account. Moreover, the two semiconductor chips can be stacked back-to-back in exact alignment, and in this case, scale reduction is achieved in the semiconductor device.
Furthermore, since the aforementioned semiconductor device can be connected simply by a wiring and mounted, the production process will be simplified, and it is desirable in some cases.
In the aforesaid semiconductor device according to the first aspect of the present invention, a lowermost semiconductor chip which is the nearest to the substrate is the first semiconductor chip, and the lowermost semiconductor chip is connected to an input/output terminal on a rear surface side of the substrate by means of a wire that passes through a through-hole formed in the substrate.
By this construction, the connection pad of the lower semiconductor chip disposed on the front surface of the substrate is connected to the input/output terminal on the rear surface of the substrate by means of a wiring, and if the upper semiconductor chip is upward oriented, it is wired to an input/output terminal on the front surface of the substrate. The aforementioned two semiconductor chips can be disposed back to back, and in this case, no restriction will be imposed on the arrangement of the connection pads in the semiconductor chip. Furthermore, since the two semiconductor chips need not be shifted from each other, the scale is reduced. Here, the front surface of the substrate refers to the surface on the side where the semiconductor chips are mounted, and the rear surface of the substrate refers to the surface on the side opposite to the front surface of the substrate.
In the semiconductor device according to the first aspect of the present invention, the second semiconductor chip is stacked adjacent to the first semiconductor chip, and has a connection pad that is positioned to face away from the substrate.
By this construction, the connection pad of the downward oriented semiconductor chip on the lower side is connected to the input/output terminal on the rear surface of the substrate by means of a wiring, and the upward oriented semiconductor chip on the upper side is wired to the input/output terminal on the front surface of the substrate. Since the aforementioned two semiconductor chips are disposed back to back, no restriction is imposed on the arrangement of the connection pads in the semiconductor chip. Furthermore, since the two semiconductor chips need not be shifted from each other, the scale is reduced.
In the semiconductor device according to the first aspect of the present invention, at least two semiconductor chips out of the two or more semiconductor chips have the same size.
By this construction, the two semiconductor chips are stacked back to back in exact alignment, so that the scale reduction of the semiconductor device is achieved. The degree of scale reduction will be particularly conspicuous in the case where three or more semiconductor chips are stacked.
A semiconductor device according to the second aspect of the present invention has a semico
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