Method for reducing mains harmonics and switching losses in...

Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C363S020000

Reexamination Certificate

active

06421256

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of electronic power converters, and more particularly to a method for improving power factor correction circuits.
BACKGROUND OF THE INVENTION
In conventional switched power converter circuits, a large input voltage filtering capacitance introduces a significant phase difference between the input voltage and the input current, and in conjunction with input rectifiers, introduces harmonic distortions in the input current signal. Since such phase shifts can create performance degradations at upstream power distribution facilities, power factor correction (PFC) circuits are often employed to minimize this reactive phase shift and bring the current and voltage signals into phase alignment.
One conventional PFC implementation uses a critical boundary mode (CBM) of operation, wherein the input filtering capacitance is eliminated to allow a sinusoidal input voltage waveform to be applied to a converter switching circuit. This switching circuit comprises a power switching device that alternately turns on and off to charge and discharge a magnetic component, such as a transformer. A ratio of the on and off times periods of the converter provides a transformed voltage to an output of the magnetic component. Since the input voltage is not buffered, input current is shaped, such that it is in phase and proportional to the input voltage.
Disadvantageously, such applications typically use a constant on-time and vary the off-time to achieve the desired timing ratio. Such a constant on-time creates distortions in the input current waveform, since a peak current in the magnetic component in a given period is a function of the voltage applied across that magnetic component. As the un-buffered input voltage envelope traces a sinusoidal waveform at a frequency in the hundreds of Hertz, a multitude of on-off switching cycles occurring at a 10 K-100 KHz frequency will each have a different input voltage and thus a different peak and average input current. This current variation creates a distortion in the envelope of the input current due to harmonic frequencies of the converter.
A simple and inexpensive configuration that is typically used for low-to-medium power applications features a single switching device and a single transformer operating in a flyback mode. The operation of a flyback converter involves turning on the switching device to impress an input voltage across the transformer. The current through the transformer will linearly rise to a predetermined value, at which time the device is turned off. The voltage on the transformer then flies back past the applied input voltage in order to linearly discharge that magnetization current back to zero. A secondary output winding of the transformer typically provides the conduction path for this discharge.
A zero-current sensing circuit, which can be implemented as an auxiliary winding in the transformer, is used to detect such a zero current condition, at which time the switching device is turned on for the next cycle. In addition to providing an appropriate regulation time for the next turn-on, the zero-current sensing circuit can also provide an optimum point for minimizing transient power dissipation in the switching device. Disadvantageously, such an auxiliary winding in the transformer adds to the cost and design complexity in the power converter.
A further disadvantage of the above effects is that they are dependent on variations in the input voltage supplied to the power converter. This dependency creates degradation in the regulation and responsiveness of the power converter.
SUMMARY
A method for reducing harmonic distortions and switching losses in a power factor correction circuit of a flyback power converter wherein optimal time periods, t
on
, t
off
, and t
d
are calculated based on the operating parameters of the power system. By balancing these three time periods, the operation of the drive circuitry can be aligned with natural resonance signals that are associated with the reactive elements of the converter. The data for deriving the three time periods can be obtained by monitoring a voltage waveform at a switched node of a transformer of the power converter.


REFERENCES:
patent: 4525774 (1985-06-01), Kino et al.
patent: 4758937 (1988-07-01), Usui et al.
patent: 5264780 (1993-11-01), Bruer et al.
patent: 5535112 (1996-07-01), Vazquez Lopez et al.
patent: 5991172 (1999-11-01), Jovanovic et al.
patent: 5995383 (1999-11-01), Poon et al.
patent: 0505982 (1992-09-01), None
patent: 0757428 (1997-02-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for reducing mains harmonics and switching losses in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for reducing mains harmonics and switching losses in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing mains harmonics and switching losses in... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2848833

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.