Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2000-10-11
2002-05-28
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S310000, C327S314000, C326S026000
Reexamination Certificate
active
06396331
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to electronic circuits, and is particularly directed to a parasitic component-based anomaly-compensating by-pass circuit that may be incorporated in one or more locations of an integrated circuit, for the purpose of minimizing undesirable effects of parasitic components, such as a parasitic capacitance of a controlled electronic device (e.g., transistor). As a non-limiting example, the invention may be employed to significantly reduce the effects of spurious AC signals induced in and transported over DC supply rails used to power a communication circuit, such as a subscriber line interface circuit.
BACKGROUND OF THE INVENTION
Systems employed by telecommunication service providers contain what are known as subscriber line interface circuits or ‘SLIC’s, which interface communication signals with tip and ring leads of a wireline pair serving a relatively remote piece of subscriber communication equipment. Present day SLICs are relatively low voltage integrated circuit architectures, designed to be interfaced with a variety of telecommunication circuits including those providing digital codec functionality. As such, a SLIC must conform with a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low power consumption, low noise, filtering, and ease of impedance matching programmability. To this end, it is extremely important that any unwanted signals, such as spurious high frequency AC signals be induced into DC power rails and applied to electronic circuit components biased thereby, be minimized to the extent possible, so as avoid propagating such (noise) signals through parasitic capacitance components to signal nodes that will cause interference with the operation of the circuit.
This spurious signal loading problem is diagrammatically illustrated in the reduced complexity circuit example of
FIG. 1
, which shows a bipolar (PNP) transistor
10
having its emitter-collector current flow path coupled in circuit with an output node
15
, shown as being coupled to a load device in the form of a resistor
16
referenced to ground. As a non-limiting example, transistor
10
may be part of a current mirror circuit, shown in broken lines
17
, with its base
11
coupled in common with the base of one or more other current mirror transistors of the circuit. The collector
13
of transistor
10
serves as a mirrored current output port, and the emitter
12
is coupled to receive a DC current shown as I
DC
, provided by way of a voltage (e.g., VCC) supply rail.
Also shown in
FIG. 1
is the transistor's parasitic base-collector capacitance
14
, and an AC (noise) signal source
20
that represents the spurious wide spectrum AC signals associated with the VCC power supply rail. As these spurious noise components are imparted principally across the base-collector junction of the transistor
10
, the AC noise source
20
(referenced to ground) is shown as applying an AC voltage V
AC20
across the base
11
and collector
13
through the load resistor
16
.
The AC load voltage V
16AC
across the load
16
may be approximated as:
V
16AC
=V
AC20
*(
R
16
/(
R
16
+1
/sC
14
)), (1)
or
V
16AC
=V
AC20
*(
sR
16
C
14
)/(1+
sR
16
C
14
). (2)
From equation (2), it can be seen that as spurious signal components increase, particularly at high frequencies, the AC load voltage component associated with such components also increases.
SUMMARY OF THE INVENTION
In accordance with the present invention, this problem is effectively obviated by coupling a compensating by-pass circuit in parallel with the controlled electronic device in a manner that is effective to decrease the spurious AC signal-coupling of the parasitic component, such that the amplitude of the unwanted AC noise voltage across the load element is very significantly reduced, or effectively minimized. In particular, the compensation circuit of the invention couples a matched electronic component having a parasitic component of its own, in a by-pass path with the compensated device. The parametric values of the transfer function of the electronic device in the by-pass compensation circuit are such as to attenuate the unwanted AC noise voltage across the load, by a factor that approximates the amplitude of the spurious signal, thereby effectively minimizing its unwanted contribution to the load voltage.
For the case of the circuit example of
FIG. 1
, the compensation by-pass circuit includes an auxiliary bipolar transistor, whose polarity and geometry match that of the transistor
10
. This auxiliary transistor has its base and emitter coupled in common with the emitter of the compensated transistor, and its collector coupled through an auxiliary resistor to the ground-referenced end of the load resistor. Like transistor
10
, the auxiliary transistor has a parasitic base-collector capacitance.
As the spurious AC voltage signal is tracked by the emitter of is thereby applied across the collector-base junction of the auxiliary transistor, the current flowing into the emitter of the compensated transistor may be expressed as the difference between the DC input current and the spurious voltage divided by the impedance parameters of the compensation circuit. Due to the parametric values of the transfer function of the electronic device in the by-pass compensation circuit, this implies that the collector current of the compensated transistor may be defined as a relatively large fraction of the difference between the DC input current and the product of the spurious voltage and the parasitic capacitance.
Since the current flowing through the load resistor is the sum of the current flowing through the parasitic capacitor of the compensated transistor and the current flowing out of the collector of the compensated transistor, the current through the load resistor is proportional to the difference between the spurious signal voltage and the product of the spurious signal voltage and this relatively large fraction (or attenuation factor). This results in the amplitude of the unwanted AC noise voltage across the load being very significantly reduced (minimized) over a broad range of noise frequencies. Moreover, properties of the compensated circuit are such that at lower frequencies the value of the auxiliary resistor can be effectively reduced to zero, so as to save components, without effectively reducing the relatively large attenuation factor.
REFERENCES:
patent: 4410815 (1983-10-01), Ransom et al.
patent: 4868424 (1989-09-01), Bosnyak et al.
patent: 5455523 (1995-10-01), Wallace et al.
patent: 6020764 (2000-02-01), Hada
Allen, Dyer, Doppelt Mlibrath & Gilchrist, P.A.
Intersil America's Inc.
Luu An T.
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