Delay time regulation method and delay time regulation circuit

Details Delay time regulation method and delay time regulation circuit Delay time regulation method and delay time regulation circuit

2000-05-19

2002-04-16

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S262000

Reexamination Certificate

active

06373313

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of regulating delay time and to a delay time regulation circuit for setting the delay time of a variable delay circuit to a desired value.
2. Description of the Related Art
With the advances in high-speed processing in information processing devices in recent years, signal delay has become a problem when transmitting and receiving information between LSI circuits. In particular, there exists the danger that variations in the signal delay time or temperature fluctuations between LSI circuits may prevent the establishment of synchronization of transmission clocks pulses in the I/O circuits of the LSI circuits. To solve problems caused by this type of signal delay, the prior art has proposed devices for shortening the signal delay time.
As systems have become larger in scale, however, LSI circuits are each arranged at greater distances from each other, with the result that such factors as wiring; capacitance produce delays in signal transfer despite increases in operation cycles. To guarantee reliable operation of a system, it is more important to reduce. variations in signal delay times of each LSI circuit than to shorten the signal delay time within an LSI circuit.
Generally, variations in the delay times of different LSI circuits increase due to such factors as fluctuation in power source. voltage, temperature fluctuations, changes in elapsed time, and differences in fabrication lot, while variations in the delay time of circuits within the same LSI circuit are substantially equal.
One method that has been adopted involves providing variable delay circuits within an LSI circuit and then setting the delay times of each LSI circuit so as to reduce variations in the delay times. In such a case, a delay time regulation circuit is provided in an LSI circuit for setting the delay time of the variable delay circuit to a desired value.
However, because the delay time of a variable delay circuit also changes due to such factors as temperature fluctuation in the same way as the internal circuits of an LSI circuit, the delay time regulation circuit preferably has a construction that both facilitates regulation of the delay time of the variable delay circuit and enables regulation of the delay time in accordance with temperature fluctuation even during operation of the LSI circuit.
To meet these demands, Japanese Patent Laid-open No. 264810/92 proposes a delay time regulation circuit that counts the number of pulses in a predefined time window, measures the delay time, and then uses the outcome of this measurement to correct the delay time of a variable delay circuit.
In a prior-art delay time regulation circuit such as described in Japanese Patent Laid-open No. 264810/92, however, a delay time cannot be accurately measured unless a clock is used that is of sufficiently shorter period than the delay time that is to be measured. Measuring delay time at a resolution of, for example, approximately 1 ns necessitates the construction of a circuit that operates at a clock of at least 1 GHz.
Such a circuit is normally difficult to construct. If the period of the clock used for measurement cannot be made sufficiently short, a variable delay circuit for setting to a long delay time must be incorporated in the LSI circuit, and this leads to the problem of an increase in the number of gates for use by the variable delay circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a delay time regulation method and delay time regulation circuit that are capable of regulating and correcting delay times through the use of a simple structure that employs few gates.
In the present invention for realizing the above-described objects, a plurality of clocks of different frequencies are sequentially applied to a variable delay circuit, and the amount of change in delay time with respect to change in a delay time selection signal, which is a signal for setting the delay time of the variable delay circuit, is found for each clock. The linear coefficient of the characteristic of the delay time of the variable delay circuit with respect to the delay time selection signal is found from the difference in the amounts of change with respect to the difference in the frequencies of the clocks, and the amount of offset with respect to the delay time selection signal that is characteristic of the variable delay circuit is found from the frequencies and amounts of change of the clocks. The delay time selection signal is then found from the linear coefficient and the difference between the desired delay time and the offset amount. This process enables the accurate detection of the characteristic of the delay time of a variable delay circuit with respect to a delay time selection signal.
Accordingly, the variable delay circuit can be accurately set to the desired delay time by correcting in accordance with the results of detecting the delay time of the variable delay circuit. In addition, the delay time of a variable delay circuit can be corrected with respect to variation in delay time arising from such factors as fluctuation in the power source voltage, fluctuation in temperature, change in elapsed time, and differences in fabrication lot. Furthermore, accurate delay times can be obtained with stability through periodic correction of delay times.
In addition, the incorporation of a pulse generation circuit in which output pulses rise with the rise of pulses that are applied to the above-described variable delay circuit and output pulses are reset by the rise of pulses outputted from the variable delay circuit enables pulse signals that have a pulse width that is equal to the delay time of the variable delay circuit. In other words, pulse signals having a desired pulse width can be obtained by using the delay time selection signal to set the delay time of a variable delay circuit to a desired value.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.


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patent: 5237224 (1993-08-01), DeLisle et al.
patent: 5278457 (1994-01-01), Fujita et al.
patent: 6177845 (2001-01-01), Moll
patent: 6-268490 (1994-09-01), None
patent: 7-248847 (1995-09-01), None
patent: 7-321619 (1995-12-01), None
patent: 10-108077 (1998-04-01), None

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