Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-03-03

2002-09-17

Phan, Trong (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S207000

Reexamination Certificate

active

06452824

ABSTRACT:

TECHNICAL FIELD
The present invention is generally related to a semiconductor memory device and, more particularly, to a layout arrangement of a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
The demand for higher integration density semiconductor memory devices has necessitated progressively denser patterns of bit lines, word lines, sense amplifiers, etc. This progression is shown in
FIGS. 1A-1C
.
FIG. 1A
is a schematic representation of an early generation DRAM architecture (e.g., 256 kbits to 4 Mbits) and shows memory cell arrays
10
which include memory cells (not shown) connected to bit lines BL. The bit lines BL of memory cell arrays
10
are connected to sense amplifiers
14
and the sense amplifiers are selectively coupled to I/O data lines (e.g., by a column selection signal applied to column switches) for inputting and outputting data.
FIG. 1B
is a schematic representation of a later generation DRAM architecture (e.g., 16 Mbits) and shows a plurality of memory cell arrays
20
. Each of the memory cell arrays
20
includes memory cells (not shown) connected to bit lines BL. The bit lines BL of the memory cell arrays
20
are connected to sense amplifiers which are in turn selectively connectable to local data lines (LDQs). For clarity, the sense amplifiers are not shown in FIG.
1
B. The sense amplifiers may be selectively connected to the LDQs via column switches responsive to column selection signals. The LDQs are selectively coupled to master data lines (MDQs) via switches
22
.
FIG. 1C
is a schematic representation of a still later generation DRAM architecture (e.g., 64 Mbits and beyond) and shows a plurality of memory cell arrays
30
. Each of the memory cell arrays
30
includes memory cells connected to bit lines. For purposes of clarity, the memory cells and bit lines are not shown in FIG.
1
C. As in the DRAM architecture of
FIG. 1B
, the bit lines of the memory cell arrays are coupled to sense amplifiers (not shown), the sense amplifiers are selectively connectable to the LDQs, and the LDQs are selectively connectable to the MDQs via switches
22
. The MDQs of
FIG. 1C
are arranged to cross over the memory cell arrays
30
as compared to the MDQs of
FIG. 1B
which are arranged at the periphery of the memory cell arrays. The architecture of
FIG. 1C
can be efficiently applied to highly integrated DRAMs since a wide data path formed to overlay the memory cell arrays requires less “real estate” than a wide data path formed at the periphery of the memory cell arrays as in FIG.
1
B. In addition, the architecture of
FIG. 1C
is advantageous over that of
FIG. 1B
since routing a wide data line path to the periphery of the memory cell arrays as in the architecture of
FIG. 1B
increases wiring capacitance and access time.
FIG. 2
is a detailed block diagram representation of the architecture of FIG.
1
C and illustrates that the memory cell arrays
30
include bit lines and word lines arranged to cross the bit lines. The bit lines are connected to sense amplifiers designated as “S/A”. Column selection signals control switches (not shown in
FIG. 2
) for selectively connecting the sense amplifiers S/A to the LDQs (LDQ and /LDQ in FIG.
2
). The LDQs are connected to the MDQs (MDQ and MDQ in
FIG. 2
) via switches MDQSW. The physical layout of a DRAM having an architecture such as the architecture of
FIG. 2
(or some other similar architecture) should provide for convenient connections between the LDQs and the MDQs and result in a data path which is organized for the efficient input/output of data to/from the memory device. In addition, the physical layout must provide spaces within which to implement the MDQSWs for connecting the LDQs and the MDQs. It is desirable that the provision of spaces for the MDQSWs does not result in an increase in the size of the area required to lay out the sense amplifiers. Since sense amplifiers are highly repeated structures in a semiconductor memory device, even the requirement of a slight increase in the size of the area for laying out the sense amplifiers can result in an undesirable increase in the size of the memory device. One layout design which provides space for the placement of the MDQSWs is described in U.S. Pat. No. 5,636,158, the contents of which are incorporated herein by reference in their entirety. In the '158 patent, bit line portions between adjacent memory cell arrays are bent as shown in
FIG. 3
to provide a space between a pair of sense amplifiers. The MDQSWs and other sparse devices may be placed in this space. However, the bending of the bit lines to form the switch region shown in
FIG. 3
results in certain limitations in the degree to which the spacing “S” between the adjacent cell arrays can be shrunk. In addition, the slanting or bending of the bit line portions can result in difficulties in the lithography and etching processes used in manufacturing the memory device. For example, slanted or bent features are more difficult to process than straight features using the current state-of-the-art off-axis illumination techniques for the manufacturing process of 256 Mbit DRAMs. This adversely impacts on the ability to mass produce devices having such slanted or bent features.
Accordingly, it would desirable to provide a layout for a highly integrated semiconductor memory device such as a DRAM which provides, among other things, for convenient connections between local data lines and master data lines, for a data path organized for efficient data input and output and for spaces within which to implement the switches for connecting the LDQs and the MDQs. It would also be desirable to provide such a memory device which may be manufactured using processes well-suited for mass production.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns. Bit lines are coupled to the memory cells in corresponding columns and word lines are arranged to be substantially orthogonal to the bit lines, each word line coupled to the memory cells in a corresponding row. The memory cell array is divided into an odd number of sub-arrays which are spaced apart from each other in the word line direction. No bit lines and no memory cells are formed in the spaces between the sub-arrays.
In accordance with another aspect of the present invention, a semiconductor memory device includes a memory cell array comprising dynamic random access memory cells arranged in rows and columns. Bit lines are coupled to the memory cells in corresponding columns and word lines extend in a direction substantially orthogonal to the bit lines. Each word line is coupled to the memory cells in a corresponding row. The memory cell array is divided into an odd number of sub-arrays which are spaced apart from each other in the word line direction and no bit lines and no memory cells are formed in the spaces between the sub-arrays. Sense amplifiers are arranged in a sense amplifier layout and coupled to said bit lines and spaces are formed in the sense amplifier layout in correspondence with the spaces between the sub-arrays. First switching transistors are provided for selecting the sense amplifiers to input/output data to/from first data lines and second switching transistors are provided for selectively connecting the first data lines to second data lines. The second switching transistors are arranged in the spaces in the sense amplifier layout.
The number and positioning of the spaces between the sub-arrays of the semiconductor memory device of the present invention are chosen so that a sufficient number of switches (e.g., for a wide I/O DRAM) may be formed to connect the local data lines to master data lines. For example, by dividing the memory cell array into 2
n
+1 sub-arrays (n is equal to greater than one), a total of 2
n
spaces are provided within which the switches may be formed. Since it is desirable in terms of data input/output to provide 2
n
master data lines, the present inven

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