Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-12-06
2002-03-12
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S216000, C257S232000, C257S233000, C257S355000
Reexamination Certificate
active
06355949
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid state imaging apparatus with a horizontal charge transfer gate which can transfer signal charge faster.
2. Description of the Related Art
In a conventional solid state imaging apparatus, there are an individual mode in which a signal charge of each of pixels is individually outputted and an interline mode in which signal charges for a plurality of pixels adjacent to each other are collectively outputted. When the signal charges of the plurality of pixels are added and outputted, a resolution is degraded. However, it is possible to shorten a time required to output all the signal charges to thereby increase a frame rate. Both of the above-mentioned operations are necessary, when there are a case where it is desired to obtain a fine reproduction image and a case where it is desired to obtain a reproduction image having a high frame rate in the same image system. Especially in a solid state imaging apparatus having a large number of pixels in which it takes a long time to output the signal charges of all the pixels. As a result, the frame rate is decreased so that the motion of an object in a reproduction image becomes unnatural, when the motion of the object is large. Thus, when the object moves, the frame rate is desired to be higher in order to obtain a reproduction image in which the motion is natural.
As an example, a case will be described below where signal charges for four pixels of two pixels in a horizontal direction and two pixels in a vertical direction are added and outputted in a solid state imaging apparatus.
In order to add signal charges of two pixels adjacent to each other in the vertical direction, the signal charge in a vertical charge transfer register are transferred two times within a horizontal blanking period. A horizontal charge transfer register receives the signal charges corresponding to two rows from each of the vertical charge transfer registers and sequentially transfers them to an output section. The signal charges corresponding to the two pixels adjacent to each other in the vertical direction are added. Thus, the number of times of the horizontal transfer required to output the signal charges of all the pixels is half that of the case where the signal charges are individually outputted. Hence, a time required to output the signal charges of all the pixels is also half.
FIG. 1
is a sectional side view showing a wiring connection and a structure of a side section along a transfer direction of the horizontal charge transfer register
405
in the solid state imaging apparatus
400
. Referring to
FIG. 1
, signal charges of two pixels adjacent to each other in the horizontal direction are added. At this time, the timings of a pulse &phgr;H
1
L applied to a final electrode of the horizontal charge transfer register
405
and a reset pulse &phgr;R applied to a reset gate electrode are set to have the periods equal to two times of those of the drive pulses &phgr;H
1
and &phgr;H
2
applied to the transfer electrode of the horizontal charge transfer register
405
. Such a method is disclosed in, for example, Japanese Laid Open Patent Application (JP-A-Heisei 4-256364).
The horizontal charge transfer register
405
is a CCD (Charge Coupled Device). As shown in
FIG. 1
, a P-type diffusion layer
702
serving as a charge transfer region of the horizontal charge transfer register
405
is formed on a main surface of an N-type diffusion layer
701
. P
+
-type regions
703
serving as barrier sections of the charge transfer region are formed in the P-type diffusion layer
702
at the same interval along a charge transfer direction. Also, charge transfer electrodes
705
are arrayed through an insulating layer
704
on the surface of the P-type diffusion layer
702
.
Each charge transfer electrode
705
is composed of a set of an accumulation section electrode
705
A above the P-type diffusion layer
702
and a barrier section electrode
705
B above the P
+
-type region
703
. The charge transfer electrodes
705
are alternatively connected to one of two horizontal bus lines
706
. Two-phase drive pulses &phgr;H
1
and &phgr;H
2
are applied through the horizontal bus lines
706
to the respective transfer electrodes
705
. The drive pulses &phgr;H
1
and &phgr;H
2
have a phase difference of 180 degrees from each other.
A final electrode
707
, an output gate electrode
708
and a reset gate electrode
709
are formed on the insulating layer
704
in this order toward the end of the horizontal charge transfer register
405
. A pulse &phgr;H
1
L, a direct current voltage OG and a reset pulse &phgr;R are applied to the above electrodes, respectively.
A first N
+
-type diffusion layer
710
is formed in the P-type diffusion layer
702
between the output gate electrode
708
and the reset gate electrode
709
to serve as an electrode of a floating capacitor for a charge detector
407
. A second N
+
-type diffusion layer
711
is formed on a side opposite to the first N
+
-type diffusion layer
710
with respect to the reset gate electrode
709
to serve as a reset gain. The first N
+
-type diffusion layer
710
is connected to an input terminal of the charge detector
407
. On the contrary, the second N
+
-type diffusion layer
711
is fixed to a predetermined direct current potential VRD.
FIGS. 2A
to
2
D are timing charts showing the pulse signals &phgr;H
1
, &phgr;H
2
, &phgr;H
1
L and &phgr;R applied to the transfer electrodes, the final electrode and the reset gate electrode of the horizontal charge transfer register
405
. The timing charts show the pulse signals when the signal charges of the respective pixels are individually outputted. the drive pulse signals &phgr;H
1
and &phgr;H
2
are two-phase two-value pulse signals which are out of phase by 180 degrees from each other. The pulse signal &phgr;H
1
L has the same phase as the drive pulse signal &phgr;H
1
. In
FIGS. 2A
to
2
D, a level HL indicates a low level of the drive pulse signals &phgr;H
1
and &phgr;H
2
and the pulse signal &phgr;H
1
L, and a level HH indicates a high level of the drive pulse signals &phgr;H
1
and &phgr;H
2
and the pulse signal &phgr;H
1
L. Also, levels RH and RL indicate the high level and low level of the reset pulse signal &phgr;R.
FIGS. 3A
to
3
D are diagram showing the accumulation states of the signal charges and the potentials along the transfer direction of the horizontal charge transfer register
405
at the respective times t
1
to t
3
of
FIGS. 2A
to
2
D.
FIG. 3A
schematically shows the horizontal charge transfer register
405
.
FIGS. 3A
to
3
D show the states of the signal charge CS and potential distributions at the respective portions of the horizontal charge transfer register
405
, for each of the times t
1
to t
3
.
The signal charges CS are individually transferred through the charge transfer registers
705
to the first N
+
-type diffusion layer
710
serving as the electrode of floating capacitance. Thus, the voltage conversion is performed to the signal charges SC. Then, the voltage is outputted from the output terminal
408
through the charge detector
407
of the solid state imaging apparatus to an external unit. After that, the signal charges of the first N
+
-type diffusion layer
710
are sent out to the second N
+
-type diffusion layer
711
serving as the reset drain, when the pulse signal &phgr;R is applied to the reset gate electrode
709
.
A case of adding and outputting signal charges of two pixels adjacent to each other in a horizontal direction will be described below.
FIGS. 4A
to
4
D are timing charts showing the pulse signals applied to the transfer electrode, the final electrode and the reset gate electrode of the horizontal charge transfer register
405
.
FIGS. 5A
to
5
E are diagrams showing the accumulation states of the signal charges and the potentials along the transfer direction of the horizontal charge transfer register
405
at the respective times t
1
to t
4
of
Dickey Thomas L
Tran Minh Loan
Young & Thompson
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