Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-07-07
2002-01-22
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S613000
Reexamination Certificate
active
06340608
ABSTRACT:
BACKGROUND OF THE INVENTION
Semiconductor chips with copper interconnect termination pads are now readily available in the market. These are mostly packaged utilizing flip-chip, Chip-on-Board, and Micron Metal Bonding using small eutectic solder bumps or ball joint material. Solder joint fatigue and life of the joint is dominated by the coefficient of thermal expansion mismatch of the solder metal, wetting material, and the substrate metal pad. The present invention overcomes these limitations by providing a technique for packaging and chip assemblies using low cost materials and superior technology.
U.S. Pat. No. 5,923,955 to Wong describes a process for creating a flip-chip bonded combination for a first and second integrated circuits using a Ni/Cu/TiN structure.
U.S. Pat. No. 5,891,756 to Erickson describes a method for forming a solder bump pad, and specifically to converting a wire bond pad of a surface-mount IC device to a flip-chip solder bump pad such that the IC device can be flip-chip mounted to a substrate. The method uses a Ni layer over the pad.
U.S. Pat. No. 5,795,818 to Marrs describes a method of forming an interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate. The method uses coined ball bond bumps.
U.S. Pat. No. 5,904,859 to Degani describes a method for applying under bump metallization (UBM) for solder bump interconnections on interconnection substrates. The UBM comprises a Cu, Cu/Cr, Cr multilayer structure.
U.S. Pat. No. 5,767,009 to Yoshida et al. describes a method of reducing cross talk noise between stacked semiconductor chips by the use of a chip on chip mounting structure.
U.S. Pat. No. 5,804,876 to Lake et al. describes a low contact resistance electrical bonding interconnect having a metal bond pad portion and conductive epoxy portion.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of bonding a chip to a substrate without the use of a multilevel component of an adhesive layer, barrier metal layer, cap layer and wetting metal layer.
Another object of the present invention is to provide a method of bonding a chip to a substrate by low cost, low inductance and low capacitance connections.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
FIGS. 1 through 10
schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
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Aliyu Yakub
Chooi Simon
Gupta Subhash
Ho Paul
Roy Sudipto Ranendra
Chartered Semiconductor Manufacturing Ltd.
Fourson George
Pham Thanh V
Pike Rosemary L. S.
Saile George O.
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