Vertical heterojunction bipolar transistor

Details Vertical heterojunction bipolar transistor Vertical heterojunction bipolar transistor

1999-11-17

2002-07-23

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C257S183000, C257S198000, C257S200000

Reexamination Certificate

active

06423990

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to heterojunction bipolar transistors (HBTs).
BACKGROUND OF THE INVENTION
Heterojunction bipolar transistors (HBTs) theoretically provide advantages over conventional homojunction bipolar transistors by providing a heterojunction between a base and emitter of a transistor. A heterojunction is formed between two dissimilar semiconductor materials. Silicon (Si) exhibits a bandgap of around 1.12 eV, but a Si homojunction has no bandgap discontinuity at the junction. A bandgap discontinuity can occur at a junction by using dissimilar semiconductor materials on opposing sides of the junction. From the perspective of an NPN transistor, discontinuity in the valence band restricts hole flow from the base to the emitter, thus improving emitter injection efficiency and current gain. To the extent that injection efficiency and current gain improvements can be achieved, base region resistivity may be lowered (which lowers the base resistance) and emitter region resistivity may be raised (which lowers base-emitter junction capacitance) to create fast transistors without significantly compromising other device parameters. Such fast transistors would be useful for high speed digital, microwave and other integrated circuit and discrete transistor applications.
In practice, HBT performance often falls far short of the theoretical expectations. One conventional Si-based HBT reduces the bandgap of the base region by creating a base material having a narrower bandgap than Si. In particular, a small amount of germanium (Ge) is mixed with Si in the base (Si
1-x
Ge
x
), and the emitter is more purely Si. Unfortunately, the amount of bandgap difference (&Dgr;Eg) for as much as 20% Ge content in the base is only about 0.15 eV. This small &Dgr;Eg achieves only a small portion of the performance benefits that HBTs theoretically promise.
Slight improvements in HBT performance have been achieved by using materials other than Si for the emitter of an HBT. Three emitter materials which have been investigated for use in HBT transistors are silicon carbide (SiC), which has a bandgap of 2.93 eV, gallium arsenide (GaAs) which has a bandgap of 1.42 eV, and gallium phosphide (GaP), which has a bandgap of 2.24 eV. Unfortunately, such materials have lattice constants which differ from Si. For example, SiC has a 20% lattice mismatch, GaAs has a 4% lattice mismatch, and GaP has a 0.34% lattice mismatch. Likewise, such materials have thermal expansion coefficients which differ from Si. SiC has a thermal expansion coefficient of about 2.6×10
−6
(°C.)
−1
, while GaAs has a thermal expansion coefficient of around 6.7×10
−6
(° C.)
−1
, and GaP has a thermal expansion coefficient of around 5.91×10
−6
(° C.)
−1
. Because of these differences, only thin layers of these materials have been successfully grown on Si without the formation of significant defects. The maximum thickness for a low defect layer of SiC grown on Si is only a few angstroms (Å) and for GaAs grown on Si is less than 200 Å. At these thicknesses or less, strain which is caused by lattice mismatch is contained by lattice stretching rather than crystal defects. Thinner, low-defect thicknesses of these materials do not possess a sufficient thickness to protect the base-emitter junction from shorting due to diffusion of metal from the emitter contact region. Thicker, high-defect thicknesses of these materials exhibit degraded junction performance due to an excessive number of defects.
The most successful HBT improvements to date are believed to have been achieved by forming a GaP layer over Si at the base-emitter junction. GaP is desirable because it has a relative large bandgap (i.e. about 2.24 eV) and little lattice mismatch with silicon (i.e. about 0.34%). Nevertheless, such conventional HBTs that use a GaP layer over Si still achieve only a small portion of the performance benefits that HBTs theoretically promise. The reason for this poor performance appears to be that a Si—GaP junction suffers from an unusually large amount of interdiffusion, where the Ga and P readily diffuse into the Si, and vice-versa. The interdiffusion between Si and GaP results in a poor semiconductor junction, with the metallurgical junction being displaced from the electrical junction. Accordingly, the performance gains that are suggested by the wide bandgap difference between a Si base and a GaP emitter are not achieved in practice because the resulting diffuse junction negates those potential gains.
In the field of photoelectric semiconductors, it is desirable to form compound structures using a Si substrate and direct gap semiconductor materials. A Si substrate is desirable for mechanical stability and because a manufacturing infrastructure exists for reliably mass producing rugged Si wafers at relatively low cost. The Si substrate is typically an extrinsic part of the photoelectric semiconductor not used in forming intrinsic photoelectric semiconductor junctions.
Compound structures using a Si substrate and direct gap semiconductor materials suffer from problems similar to those discussed above for HBTs. Namely, lattice constant and thermal expansion coefficients for direct gap semiconductors differ from Si. Consequently, in attempting to produce low-defect compound semiconductors having direct gap semiconductors and a Si substrate, conventional photoelectric semiconductors often include very thick, highly doped buffer layers between the Si substrate and direct gap materials. Such buffer layers may include indirect gap materials, such as GaP and others, but these indirect gap materials are unsuitable for intrinsic photoelectric semiconductors.
Such buffer layers tend to incrementally shift lattice constants and thermal expansion coefficients so that the intrinsic direct gap photoelectric semiconductor materials may then be grown with fewer defects. Such applications often form relatively thick buffer layers which themselves may have numerous defects, at least closer to a Si interface, that are of little consequence to the intrinsic photoelectric semiconductor. Needless to say, such buffer layers are not used in forming semiconductor junctions.
U.S. Pat. No. 5,912,481, which describes prior work of the inventors of the present invention, describes an HBT that goes a long way toward providing performance benefits that HBTs theoretically promise. However, further improvements in speed, radiation tolerance characteristics, and thermal dissipation would be desirable.
Speed and radiation tolerance characteristics can both be enhanced by using an improved substrate in which, or on which, an intrinsic transistor is formed. Conventional techniques apply a silicon on insulator (SOI) technology. Typically, an intrinsic transistor is formed over an SiO
2
layer rather than over a semiconductor, such as Si. When hit by radiation, the SiO
2
layer does not produce the electron disturbances that are characteristic of a semiconductor, leading to radiation tolerance improvements. In addition, the insulative SiO
2
layer lowers capacitance, which leads to improvements in speed. However, SiO
2
is not a particularly good thermal conductor. Consequently, less heat is conducted away from the intrinsic transistor, fewer transistors can be placed near one another on an integrated circuit, and higher power devices are not practical.
Moreover, one conventional SOI technique forms a crystalline layer (e.g., Si) used in the formation of intrinsic transistors over the SiO
2
layer. Since SiO
2
is a porous material, not a crystalline material, the overlying crystalline layer often exhibits defects that cannot be cured by annealing. Accordingly, poor yields result. Another conventional SOI technique forms a single Si crystal, then implants oxygen (O
2
) under high energy deep into the Si crystal and anneals to form a deep SiO
2
layer. Unfortunately, getting complete and uniform SiO
2
formation within an existing Si layer is extremely difficult. Consequently, this

Affiliated with

Also associated with

Rating

Vertical heterojunction bipolar transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical heterojunction bipolar transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical heterojunction bipolar transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2846988