Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-07-14
2002-04-02
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06366110
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a configuration for testing chips produced from a wafer, in which the chips are supplied with test signals through the use of a test head, and evaluation of the test signals makes it possible to ascertain whether or not a respective chip satisfies predetermined requirements.
As is known, chips must be subjected to numerous tests before being delivered to users. The tests ascertain whether or not a respective chip, or more precisely an integrated circuit provided in the respective chip, such as a memory circuit, satisfies predetermined requirements. Ever increasing integration levels or storage densities mean that the time required for the tests (test time) is becoming longer and longer, which also causes test costs to rise to an unacceptable extent.
In order to remedy that situation, it has already been thought of to no longer test the chips individually, but instead to test a plurality of chips in parallel and to additionally employ data compression in the process. That would enable the test time to be reduced by a not inconsiderable extent. The disadvantage, however, would be that such parallel testing would require a correspondingly large number of tester channels leading from the respective chips that are in parallel with one another to the test head. That would render such a procedure complicated, with the result that it has not been introduced in practice heretofore.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a configuration for testing chips, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which enables a test time for the chips to be considerably reduced without major additional outlay.
With the foregoing and other objects in view there is provided, in accordance with the invention, a test configuration, comprising a wafer having chips to be tested; the chips having sawing edges and test lines disposed in the sawing edges; a test head connected to the test lines for supplying the chips one after the other with test signals to be evaluated for ascertaining if a respective one of the chips satisfies predetermined requirements; and a dedicated chip select line for selecting one of the chips to be currently tested.
One of the test lines laid in the sawing edge can be used in each case for this chip select line, with each chip being assigned a chip select line.
With the objects of the invention in view, there is also provided a test configuration, comprising a wafer having chips to be tested; the chips having sawing edges, test lines disposed in the sawing edges and data inputs and data outputs in the sawing edges; a test head connected to the test lines for supplying a plurality of the chips in parallel, behaving like a module, with test signals to be evaluated for ascertaining if a respective one of the chips satisfies predetermined requirements; and logic units disposed at the data inputs and data outputs for data compression.
Therefore, in the configuration according to the invention, the testing of the as yet unseparated chips is actually performed at the wafer level, with the test lines being laid in the sawing edge (kerf), where they are destroyed after the conclusion of the test when the chips are sawn from the wafer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration for testing chips, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5047711 (1991-09-01), Smith et al.
patent: 5239191 (1993-08-01), Sakumoto et al.
patent: 5539325 (1996-07-01), Rostoker et al.
patent: 0427328 (1991-05-01), None
Greenberg Laurence A.
Kerveros J.
Lerner Herbert L.
Metjahic Safet
Stemer Werner H.
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