Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-07-10

2002-05-21

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C326S113000

Reexamination Certificate

active

06392467

ABSTRACT:

The present invention relates to a semiconductor integrated circuit (IC). More particularly, the present invention relates to a semiconductor IC using MOSFETs in which signals are applied to the gate and body of the MOSFETs.
BACKGROUND OF THE INVENTION
In recent years, the operating speed of a large-scale integrated circuit (LSI) has increased significantly. An LSI which operates at 500 MHZ or faster has also been disclosed. The faster the LSI operates, the larger the power consumption because the loading and parasitic capacitances are charged/dissipated at a high frequency. To resolve this problem, ways to decrease the operating voltage and power consumption while maintaining the high-speed operation capability have been studied.
Recently, a silicon-on-insulator (SOI) device technique, in which a device is fabricated on a silicon layer on an insulator layer has been proposed for the low-voltage operation of a circuit. Much effort has been made to reduce the operating voltage below 0.5V using SOI devices. SOI CMOS with gate-body connection (DTMOS) and body bias controlled SOI pass-gate logic (BCSOI) pass-gate) take advantage of individually SOI device activated area and reduce threshold voltage by controlling each device body bias. Hence, they have a higher speed than circuits based on fixed low threshold voltage. Due to draw-body junction leakage, previous attempts suffer from leakage current at supply voltage higher than 0.8V.
FIG.
15
(
a
) shows an SOI-MOSFET in which a thin silicon layer is fabricated on a silicon dioxide layer and a MOSFET device is formed thereon. In this Figure,
1
denotes an isolation layer,
2
denotes a thin silicon layer,
3
denotes a gate-insulation layer,
4
denotes a gate electrode,
5
denotes a source-drain diffusion layer, and
6
denotes a device isolation insulator layer with which bodies
2
a
and
2
b
are isolated for each of the transistors.
FIGS.
15
(
b
) and
15
(
c
) show the SOI-MOSFET in the ON or active mode. FIG.
15
(
b
) shows the fully depleted mode in which no neutral region exists in the body. FIG.
15
(
c
) shows the partially depleted mode in which a neutral region exists in the body.
In the SOI-MOSFET in FIG.
15
(
a
), the thin silicon layer
2
is isolated by means of the insulation layer
6
. This provides, for a given MOSFET, two independent bodies
2
a,
2
b
(each of which acts like a MOSFET on a bulk substrate of conventional technology). It is possible to take advantage of this and connect a gate and body in each of the MOSFETs. In nMOSFETs, a CMOS gate (e.g., inverter) dynamic-threshold voltage MOSFET called DTMOS, for example, is proposed. In the DTMOS in the ON or active mode, the threshold voltage is low because the body voltage is the source voltage. In the OFF or sleep mode, the body voltage is OV which is suited to high-speed operation at a low voltage. [See F. Assaderaghi, 1994, “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation,”
IEDM Tech Dig.,
pp. 809-812].
Also, a SIMOX-MTCMOS technique (SIMOX is one of the methods of manufacturing SOI substrates) is proposed (Douseki et al.,
ISSCC
96
Tech Dig.,
pp. 84-85). The SIMOX-MTCMOS is configured as follows:
a main circuit is constructed with an SOI-CMOS gate with a low threshold value. The leakage current is limited during the sleep mode by serially connecting a transistor with a high threshold value, which is turned off during the sleep mode, to the main circuit.
However, the following problems remain even when utilizing these techniques. In the former (DTMOS) technique, a signal potential is applied directly to the body. Therefore, if the signal potential, which is the source voltage, is higher (0.8V in a general condition) than the pn junction potential (potential difference between Fermi potential in the p-region and Fermi potential in the n-region), the point between the body (e.g., the p-type in an nMOS) and source (e.g., the n-type in an nMOS) is biased forwardly. This generates leakage current, thus impeding normal operation. FIG.
16
(
a
) shows the equivalent circuit with the gate-body connection; FIG.
16
(
b
) shows the leakage profile.
On the other hand, in the latter (SIMOX-MTCMOS) technique, as shown in
FIG. 17
, the leakage current is decreased during the sleep mode. However, because there is no means for controlling the leakage current during the active mode, the lower limit of the threshold voltage (Vt) of the main circuit remains unfavorably high. When the threshold value, which is derived from the lower limit of the leakage current during the active mode for the device shown in
FIG. 18
, is 0.15V, the threshold value in the former DTMOS technique is 0.15V during the sleep mode. The threshold value is −0.05V during the active mode. In the latter (SIMOX-MTCMOS) technique, the threshold value 0.15V is basically the same during the sleep and active modes. For this reason, the device made with the latter technique operates slower than those made with the former technique using a higher minimum operating voltage.
In addition, both the former and latter techniques use a so-called CMOS logic circuit such as an inverter, NAND logic, etc., as a semiconductor IC which comprises:
a pMOS loading circuit connected to the source power, and
an nMOS driving circuit connected to a ground potential. For this reason, both techniques have not optimized speed, power consumption, and device size.
As described, even if an SOI-MOSFET is used, it is difficult for a semiconductor IC of conventional technology to operate at a high-speed with a wide range of low voltages to consume low power.
For further attempts to solve these problems, reference is made to “Tsuneaki Fuse, Yukihito Oowaki et al, ISSCC96 Tech. Dig. pp. 88-89”.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to overcome the above-noted problems of prior-art solutions.
The apparatus incorporating the principles of the present invention solves the above problems using an SOI-MOSFET and provides high-speed semiconductor ICs which operate at a high-speed with a wide range of low voltages and consume low power.
In a preferred embodiment of the present invention, a semiconductor integrated circuit is provided having a MOSFET wherein input signals are applied to its gate and body for forming a circuit block for driving a load having a capacitance and which includes:
a transistor network and at least one buffer circuit having at least two configurations wherein a plurality of circuit blocks are formed on the same IC chip, and any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.
In a further preferred embodiment of the present invention, (1) a MOSFET is formed on a thin silicon layer formed on an insulation layer (SOI), and (2) the buffer circuit comprises:
a first buffer circuit of the CMOS inverter type using a MOSFET in which the gate and body are connected; and
a second buffer circuit of the pMOS feedback type in which a pMOSFET and an nMOSFET are serially connected;
the gate-body of the nMOSFET and the body of the pMOSFET are connected to the network output. The gate of the pMOSFET is connected to a complementary output wherein, when the loading capacitance is at least a predetermined value, the first buffer circuit is selected, and when the loading capacitance is smaller than the predetermined value, the second buffer circuit is selected.
In another preferred embodiment of the present invention, the buffer circuit comprises a first buffer circuit of the CMOS inverter type using a MOSFET in which the gate and body are connected, and
a second buffer circuit with a pMOS flip-flop latching relay circuit formed at the CMOS inverter type input portion of the buffer circuit using a MOSFET in which a gate and a body are connected, wherein
when the loading capacitance is at least a predetermined value, the first buffer circuit is selected, and
when the loading capacitance is smaller than the predetermined value, the second buffer circui

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