Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-02-23
2002-05-28
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185300
Reexamination Certificate
active
06396739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a reference voltage generator, and in particular to a stable reference voltage generator utilizing flash memory transistors which is particularly applicable for flash memory applications.
2. Description of Related Art
There are many applications for voltage reference generators which are stable regardless of changes in ambient temperature and supply voltage. Such devices have application in oscillator, timer and voltage regulation circuitry.
Flash memory arrays with precise on-chip voltage regulation require stable voltage references. Typically, voltage reference generators are fabricated-as a part of the fabrication of the flash memory integrated circuit array. It is therefore desirable for such a reference voltage generator to be constructed using the same CMOS fabrication techniques utilized for making the remainder of the flash memory array.
One such reference voltage generator which uses flash memory cells in conjunction with a flash memory array is described in U.S. Pat. No. 5,339,292 entitled “Precision Voltage Reference.” This patent describes a voltage reference circuit which includes a pair of flash memory cells, each having a different charge on the respective floating gates. Circuitry is provided for connecting each of the flash cells in parallel circuits in which equal currents are generated in an equilibrium condition. A circuit is provided for generating a voltage indicative of the current in each of the pair of parallel circuits. A differential amplifier responsive to the voltages in the parallel circuits, provides an output voltage to vary the current through the flash memory cells to bring the currents through the respective parallel paths into equilibrium, and to maintain constant reference voltage.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a precision voltage reference for a MOS or CMOS integrated circuit which contains flash memory cells.
Another object of the present invention is to provide a stable voltage reference generator, for use in a flash memory array, which uses flash memory cells as a part of the reference voltage generator circuitry.
Another object of the invention is to provide a reference voltage generator which is more stable with temperature and power variations then previous reference voltage generators utilizing flash memory cells.
Another object of the invention is to provide a reference voltage generator, using flash memory cells, wherein the magnitude of the reference voltage is determined by the difference in threshold values of the respective flash memory cells.
These and other objects of the present invention are realized in a reference voltage generator utilizing flash memory cells, each having a source, drain, floating gate and control gate. First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is “over-erased” until it has a negative threshold voltage, so that the first flash memory transistor is rendered permanently conducting.
Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium. If variations in the output voltage are sensed the currents through the flash memory transistors are varied to bring the currents into equilibrium.
In the over-erased state the first flash memory transistor is permanently conducting. This is important in maintaining stable conditions regardless of changes in ambient temperature and power supply variations.
In accordance with another aspect of the invention, the control gate of the first (over-erased) flash memory transistor is connected to the system ground, V
ss
. This further increases the stability of the reference voltage generator of the present invention.
In accordance with another aspect of the invention, the charges on the floating gates of the first and second flash memory transistors are maintained and not disturbed. This is accomplished by keeping the first and second flash memory transistors in the linear region of operation by providing appropriate biasing circuitry and keeping the source/drain voltage stable and small.
REFERENCES:
patent: 5233562 (1993-08-01), Ong
patent: 5335198 (1994-08-01), Buskirk et al.
patent: 5339272 (1994-08-01), Tedrow et al.
patent: 5477499 (1995-12-01), VanBuskirk et al.
patent: 5859526 (1999-01-01), Do
Drake E. E.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Zarabian A.
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