Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-06-07

2002-04-16

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S141000

Reexamination Certificate

active

06373307

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit having a delay circuit used for generating a synchronization signal (hereinafter, called a clock signal).
2. Background Art
Conventionally, in the semiconductor integrated circuit operated in synchronism with a clock signal, the external clock signal
1
is received by a signal receiving circuit
10
and is amplified by an amplification circuit
40
for generating an internal clock signal
4
to be used for a circuit
50
for controlling the clock signal.
FIG. 8
is a block diagram showing the schematic structure of a conventional semiconductor integrated circuit.
As shown in
FIG. 9
, a delay time T
D
is generated between the external clock signal
1
and the internal signal
4
in the course of being received by the receiving circuit
10
and amplified by the amplification circuit
40
.
FIG. 9
is a diagram showing a timing chart of a clock used in the conventional semiconductor integrated circuit.
The delay time tends to increase because the scale of the circuit required for the semiconductor integrated circuit increases as the manufacturing technology advances. At the same time, as the operational speed of the system installed with such an integrated circuit increases, the operational speed of a clock cycle in which the semiconductor integrated circuit operates also increases. As a result, the delay time T
D
occupies a relatively large portion in the clock cycle T
C
, which results in hindering the operation of the circuit.
An example of one of the conventional measures for reducing the increase of the delay time T
D
in the clock cycle T
C
is to use a phase locked loop (hereinafter, called PLL).
As the operational speed of computers increases, the data transfer speed of the semiconductor memory device becomes a speed limiting factor of the system performance. In order to improve the data transfer speed of the semiconductor memory devices, an operational specification is proposed, which is termed the double data rate, for executing an input and output operation twice within one clock cycle.
FIG. 10
shows a timing chart when the double data rate is executed. In the double data rate operation, an order signal and an address signal are input at a rise of the clock signal, and the data input and output signals are input and output at an intermediate timing between the rise and fall of the clock signal.
That is, in the double data rate operation, the order signal Com and the address signal Add are input at the rise of the clock signal CLK, and the data input and output signal is carried out by inputting a data DQ at an intermediate timing between the rise and fall of the clock signal. It is advantageous to adopt such a specification regarding the double data rate operation, since, when the frequency of the clock is 66 MHz, it is possible to obtain a data transfer speed of 132 Mbits/sec, corresponding to twice the transfer frequency of 66 MHz, while the clock frequency of the operational frequency of the data signal is maintained at the same transmission speed of 66 MHz, the same as that of the operational frequency of the clock signal. Thus, such a double data rate operation is now being adopted in future high speed DRAMs such as a high speed SRAM, a synchronous DRAM, and a sink link DRAM (Nikkei Microdevice February issue, p. 11, 1997). The double data rate specification is generally wide spread in the wide fields of technology not only for use in the semiconductor devices but also being adopted for the APG specification defined for high speed data transfer
15
between a graphics controller LSI and a system controller LSI (“Accelerated Graphics port Interface Specification” Revision, 1.0, Intel Corporation, Jul., 31, 1996).
Here, the reason for not adopting the rise and fall of the clock signal as the standard in the double data rate specification is because the cycle time of the operation of the semiconductor integrated circuit becomes unstable as the clock cycle time decreases. As the clock cycle time decreases, the transition time of the clock signal ceases to be negligibly small, and the waveform consisting of the rise and the fall of the waves becomes asymmetric, which results in causing unequal cycle times because the period at high voltage and the period at low voltage in regard to the input threshold voltage becomes unequal.
Conventionally, the PLL integrated with a dividing circuit has been used for realizing the double data rate specification. The PLL is operated so as to generate an internal clock signal and to making the phase difference between the internal clock signal and the external clock signal into zero. However, the problem arises that the power consumption of the PLL increases, since it takes more than ten cycles and, accordingly, since it is necessary to operate the PLL continuously in order to use an internal clock signal having no phase difference with the external clock signal at a desired timing. The increasing power consumption causes a larger problem in the semiconductor memory devices, particularly in the case of a plurality of dynamic RAMs, used as the main memory components in a computer system. Furthermore, another problem arises in that the accuracy of the control frequency is lowered, since the oscillating operation is controlled by the voltage since the voltage control oscillator
62
is controlled by the voltage.
A few methods for solving the above problems have been proposed, such as RDLL (Register-Controlled Delay-Locked Loop) or SMD (Synchronous Mirror Delay). The details of these methods are described in IEICE Trans. Electron. Vol 1, No. 6, pp. 798-807, and in Japanese Patent Application, First publication No. 8-237091. A method to provide the double data rate specification using these techniques has also been proposed.
The double data rate specification can be provided by use of these RDLL and SMD. Since the times required for removing the phase difference between the internal clock signal and the external clock signal in the RDLL and the SMD are one cycle and two cycles, respectively, it is not necessary to operate the circuit continuously. Thus, since it is possible to stop the operation of the circuit when the internal clock signal
4
is not used, and since the power is not necessary while the circuit is on standby, the power consumption can be reduced. In addition, the RDDLL and the SMD are not provided with the voltage control oscillator for controlling the oscillation so that the control frequency can be maintained accurately irrespective of the power source voltage.
However, the RDLL and the SMD still have a problem in that these circuits cannot afford sufficient operational freedom for the time window getting narrower due to the dispersion of the generation timing of the internal clock signal by the dispersion of the cycle time.
To sum up, in the semiconductor integrated circuit, timings of the input and output signals are prescribed by the clock input signal. That is, when the data input signal DQ is latched by the clock input signal CLK, as shown in
FIG. 10A
, the time for preserving the data input signal before and after the clock input signal, that is, the input setting time t
S
and the input holding time t
h1
, are provided.
As shown in
FIG. 10B
, when outputting the data, an access time t
a
, the time until the data output signal is fixed, and an output holding time t
h2
, the time for holding the previous data output signal, are decided. The resolution of the RDLL is determined by one delay circuit, corresponding to the two gate levels, which is the minimum unit that can be set by the shift register. The resolution of the SMD circuit is the two gate levels.
Accordingly, the timing of the internal clock signal with respect to the external clock varies within the resolution, that is, within a range of time propagating the two gate levels. Rules of the input/output timings of the input setup time t
S
, the input holding time t
h1

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