Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-01-24
2002-05-14
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S145000
Reexamination Certificate
active
06388599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a reference voltage generator circuit for generating a reference voltage or voltages to be used in a converter, such as an A/D or a D/A converter, and more particularly, to a generator circuit for providing reference voltages to a plurality of systems.
2. Description of the Related Art
As shown in
FIG. 1
, a conventional reference voltage generator circuit
10
comprises a rough resistor bank
11
including a pair of resistors RI of an equal resistance, and a first and second fine resistor bank
12
,
13
each including four resistors R
2
of an equal resistance.
The resistors R
1
are connected in series between a high potential side reference voltage V
ref1
, and a low potential side reference voltage V
ref2
. The first resistor bank
12
is connected in shunt with the resistor R
1
located toward the reference voltage V
ref1
, and the second resistor bank
13
is connected in shunt with the resistor R
1
located toward the reference voltage V
ref2
. Each of the resistor banks
12
,
13
includes four resistors R
2
connected in series.
A potential difference between the reference voltages V
ref1
, V
ref2
is equally divided across each resistor R
1
, and the voltage across each resistor R
1
is divided into four equal fractions across each resistor R
2
. Nodes N
1
to N
9
are defined at junctions between each resistor R
1
and its adjacent resistor R
2
as well as at junctions between respective adjacent resistors R
2
in the order of descending potential, as shown.
Each of the nodes N
1
to N
3
is connected to a circuit A
1
in a subsequent stage via respective switches SA
1
, and is also connected to a circuit B
1
in a subsequent stage via respective switches SB
1
. Each of the nodes N
3
to N
5
is connected to a circuit A
2
in a subsequent stage via respective switches SA
2
, and is also connected to a circuit B
2
in a subsequent stage via respective switches SB
2
. Each of the nodes N
5
to N
7
is connected to a circuit A
3
in a subsequent stage via respective switches SA
3
, and is also connected to a circuit B
3
in a subsequent stage via respective switches SB
3
. Each of the nodes N
7
to N
9
is connected to a circuit A
4
in a subsequent stage via respective switches SA
4
, and is also connected to a circuit B
4
in a subsequent stage via respective switches SB
4
. The circuits A
1
to A
4
and the circuits B
1
to B
4
(not shown) are comparators associated with independent A/D converters.
A select signal generator circuit
14
generates select signals &phgr;A
1
to &phgr;A
4
and &phgr;B
1
to &phgr;B
4
which actuate corresponding switches SA
1
to SA
4
and SB
1
to SB
4
. Thus, each of the switches SA
1
to SA
4
and SB
1
to SB
4
is turned on or off in response to a corresponding one of the select signals (&phgr;A
1
to &phgr;A
4
and &phgr;B
1
to &phgr;B
4
. In this manner, potentials at the respective nodes N
1
to N
9
are provided as reference voltages to the circuits A
1
to A
4
and B
1
to B
4
.
It is to be noted that as the selected switches SA
1
to SA
4
and SB
1
to SB
4
are turned on or off, switching noise occurs. For example, assuming that the switches SA
1
are turned on in response to the select signal &phgr;A
1
, if the switches SB
1
are then turned on in response to the select signal &phgr;B
1
, the operation of the switches SB
1
produces switching noises at the nodes N
1
to N
3
. In this instance, the node N
3
exhibits a higher impedance with respect to the reference voltages V
ref1
, V
ref2
than the nodes N
1
, N
2
, and consequently a noise level at the node N
3
is higher than at the nodes N
1
, N
2
. This causes an unstable reference voltage of a reduced accuracy to be provided to the circuit A
1
connected to the node N
3
, such that the circuit A
1
may malfunction.
To overcome such a problem, a separate reference voltage generator circuit
10
may be provided for each group of circuits A
1
to A
4
and B
1
to B
4
. when so arranged, there is only one switch associated with each node, thus avoiding adverse influences of one of the switches upon another of the switches.
However, such an arrangement has greatly increased circuit area. In addition, the high potential side and the low potential side reference voltages must be provided to individual reference voltage generator circuits, and accordingly, the reference voltages may vary from reference voltage generator circuit to reference voltage generator circuit due to wiring resistances, resulting in a variation in the magnitude of reference voltages provided to the individual reference voltage generator circuits. In order to reduce such a variation in the reference voltages, it is preferred that common reference voltages be delivered in parallel from a single reference voltage generator circuit.
It is an object of the present invention to provide a reference voltage generator circuit capable of providing a stable reference voltage.
SUMMARY OF THE INVENTION
To achieve the above objective, the present invention provide a reference voltage generator circuit for delivering a reference voltage to a plurality of systems including a first system and a second system, comprising: a rough resistor bank including at least one resistor connected in series between a high potential side reference voltage and a low potential side reference voltage; a first fine resistor bank including a plurality of resistors connected in shunt with at least on resistor of the rough resistor bank; a second fine resistor bank including a plurality of resistors connected in shunt with the at least one resistor in the rough resistor bank; a first group of switches connected between nodes between respective resistors in the first fine resistor bank and the first system; and a second group of switches connected between nodes between respective resistors in the second fine resistor bank and the second system.
The present invention further provides a reference voltage generator circuit for delivering reference voltages to a plurality of systems including a first system and a second system, comprising: a first rough resistor bank including at least one resistor and a second rough resistor bank including at least two resistors, the first and second rough resistor bank connected in parallel with each other between a high potential side and a low potential side reference voltage; a first fine resistor bank connected between the first and second rough resistor banks and connected in shunt with the at least one resistor bank in the first rough resistor and extending between the at least one resistor and a junction between at least two resistors in the second rough resistor bank; a second fine resistor bank connected in parallel with the first fine resistor bank; a first group of switches connected between nodes between adjacent resistors in the first fine resistor bank and the first system; and a second group of switches connected between nodes between adjacent resistors in the second fine resistor bank and the second system.
The present invention provides a reference voltage generator circuit for delivering reference voltages to a plurality of systems including a first system and a second system, comprising: a rough resistor bank including at least two resistors connected in series between a high potential side reference voltage and a low potential side reference voltage; a first fine resistor bank including a plurality of series connected resistors connected in shunt with one of the resistors in the rough resistor bank; a second fine resistor bank including a plurality of series connected resistors connected in shunt with one of the resistors in the rough resistor bank; a first group of switches connected between nodes between adjacent resistors in the first fine resistor bank and the first system; a second group of switches connected between nodes between adjacent resistors in the second fine resistor bank and the second system; and a selection circuit for selectively connecting each of the first and second fine resistor banks to
Mizuguchi Toshitaka
Yamamoto Katsuyoshi
Armstrong Westerman Hattori McLeland & Naughton LLP
Wamsley Patrick
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