Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

2000-08-15

2002-04-09

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000

Reexamination Certificate

active

06369625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit. More particularly, the invention relates to a PLL circuit varying a repetition frequency of an output signal depending upon a result of comparison of an input signal having a reference frequency (hereinafter referred to as “reference input signal”) and an output signal having a dependent frequency to depend on the reference input signal.
2. Description of the Related Art
In general, as shown in
FIG. 15
, a PLL circuit includes a phase comparator
1
performing phase comparison with a reference input signal and a voltage controlled oscillator
3
(hereinafter referred to as “VCO”) varying oscillation frequency depending upon a result of phase comparison, and feeds back an output signal
300
of the VCO
3
to the phase comparator
1
as an object for phase comparison. In this case, a signal indicative of the result of phase comparison of the phase comparator
1
is converted into a voltage level smoothed by a low pass filter
2
(hereinafter referred to as “LPF”). By the voltage level, variation of an oscillation frequency of the VCO
3
is controlled.
On the other hand, the output signal
300
output from the VCO
3
becomes a dependent frequency signal
400
by frequency division into N by a frequency divider
4
and is input to the phase comparator
1
. On the other hand, the reference input signal
100
becomes a reference input signal
500
by a frequency division into N by a frequency divider
5
and is input to the phase comparator
1
. As set forth above, in practice, phases are compared with respect to frequency divided signals, i.e. the reference input signal
500
and the dependent frequency signal
400
for controlling the oscillation frequency depending upon the result of phase comparison.
In the PLL circuit, even when a phase relationship between the reference input signal and the dependent frequency signal is constant under a condition where an operation environment is constant, the dependent frequency signal is varied by variation of operation environment due to variation of power source fluctuation and variation of environmental temperature. Therefore, as a result, fluctuation is caused due to phase difference between the reference input signal and the dependent frequency signal. Upon changing data by establishing synchronization of data which is synchronized with the reference input signal, with the dependent frequency signal, changing of data becomes more difficult at higher speed data to be a cause of data error. On the other hand, when an alarm output is used in data processing, high precision becomes necessary as demanded to possibly be influenced by noise due to external disturbance or so forth.
The conventional PLL circuit as set forth above, encounters a problem to cause data error due to variation of the dependent frequency signal for variation of operation environment caused by fluctuation of the power source and variation of environmental temperature to result in fluctuation of phase difference between the reference input signal and the dependent frequency signal, and if fluctuation of the phase difference is caused, upon changing data by establishing synchronization of data which is synchronized with the reference input signal, with the dependent frequency signal, changing of data becomes more difficult at higher speed data to be a cause of data error.
SUMMARY OF THE INVENTION
The present invention has been worked out in view of the problem set forth above. It is therefore an object of the present invention to provide a PLL circuit which can reduce possibility of occurrence of data error even with a high speed data and reduces influence of noise, due to external disturbance or the like.
According to one aspect of the present invention, a phase locked loop circuit comprises:
phase difference detecting means for detecting a phase difference of an output signal in relation to an input signal;
oscillation means for outputting an output signal having a repetition frequency corresponding to a voltage level of a phase difference signal representative of the phase difference detected by the phase difference detecting means; and
control means active when phase advanced condition or phase retarded condition of the output signal relative to the input signal is continued, for control a voltage level of the frequency difference signal depending upon number of times where phase advanced condition or phase retarded condition of the output signal relative to the input signal is continued.
The control means may include a pulse width modulator for generating a pulse width corresponding number of times where phase advanced condition or phase retarded condition of the output signal relative to the input signal is continued, and an integration circuit for integrating a pulse width modulated pulses, an integrated output level of the integration circuit is added to the phase difference signal.
The pulse width modulator may include an up/down counter performing counting up or counting down operation when phase advanced condition or phase retarded condition of the output signal in relation to the input signal is continued and otherwise performing opposite operation, for generating the pulse having the pulse width corresponding to the count value.
The phase locked loop circuit may further comprise temperature detecting means for detecting temperature variation and an adder circuit adding the integrated output level controlled addition characteristics to be constant depending upon the detected temperature to the phase difference signal. In this case, the temperature detecting means is a thermistor variable of resistance value according to a predetermined temperature characteristics, the thermistor is so selected to as cancel variation of resistance value of a resistor forming the adder circuit by variation of resistance value therein.
The phase locked loop circuit may further comprise an alarm means for externally feeding an alarm when the phase difference of the output signal in relation to the input signal becomes greater than or equal to a predetermined value.
The phase difference may be greater than or equal to the predetermined value, is maintained for a given period or longer.
The phase locked loop circuit may further comprise an oscillator generating an oscillation signal having a substantially the same repetition frequency as a repetition frequency of the input signal, and a switching circuit responsive to interrupted condition of the input signal continued for a predetermined period for inputting the oscillation signal of the oscillator to the phase difference detecting means and the control means in place of the input signal. In this case, upon switching from the input signal to the oscillation signal by the switching circuit, and alarm means externally feeding an alarm indicative of switching of input from the input signal to the oscillation signal.
The phase locked loop circuit may further comprise a first counter performing a counting operation when the input signal is low level, a second counter performing counting operation when the input signal is high level; first clear means for clearing the first counter when the count value of the first counter reaches a predetermined value, a second clear means for clearing the count value of the second counter when the count value of the second counter reaches the predetermined value, and an alarm output means for outputting an alarm when at least one of the first and second counter reaches the predetermined value.
In short, the PLL circuit according to the present invention detects the phase difference of the input signal having the reference input signal and the output signal having the dependent frequency signal for generating a pulse width modulated signal having a pulse width corresponding to the detected value. Thus, reaction against variation of the phase is performed quickly to reduce the phase shifting amount and steady phase error fluctuation. Also, when the phase difference greater than t

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