Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-05-02
2002-07-09
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S525000
Reexamination Certificate
active
06417726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device including a power supply circuit for generating an internal power supply potential from an externally applied potential.
2. Description of the Background Art
In general, semiconductor memory devices that are currently produced, in particular, dynamic random access memories Hereinafter, referred to as DRAMs), include an internal power supply generating circuit for stabilizing an external power supply potential by boosting or down-conversion so as to generate an internal power supply potential.
FIG. 22
is a block diagram showing the schematic structure of an internal power supply generating circuit
538
included in a conventional DRAM.
Referring to
FIG. 22
, the internal power supply generating circuit
538
includes a constant current control circuit
542
for outputting potentials V
2
, Viconst and Vbias, a reference potential generating circuit
544
for receiving the potentials V
2
and Viconst and outputting a reference potential Vrefp, a Vccp generating circuit
546
for receiving the potential Vbias from the constant current control circuit
542
and the reference potential Vrefp from the reference potential generating circuit
544
and outputting an internal power supply potential Vccp, and an observing pad
548
connected to a node receiving the internal power potential Vccp, for monitoring a potential during wafer testing.
The internal power supply generating circuit
538
further includes a reference potential generating circuit
550
for receiving the potentials V
2
and Viconst and outputting a reference potential Vrefa, a Vcca generating circuit
552
for receiving the potential Vbias and reference potential Vrefa and outputting an internal power supply potential Vcca, and a pad
554
connected to a node receiving the internal power supply potential Vcca, for observing a potential during wafer testing.
The internal power supply generating circuit
538
further includes a reference potential generating circuit
556
for receiving the potential V
2
from the constant current control circuit
542
and outputting a reference potential Vref
1
, a VPP generating circuit
558
for outputting an internal power supply potential VPP according to the reference potential Vref
1
, and a pad
560
connected to a node receiving the internal power supply potential VPP, for observing a potential during wafer testing.
The internal power supply generating circuit
538
further includes a reference potential generating circuit
562
for receiving the potential Vbias and outputting a reference potential Vref
2
, a VBB generating circuit
564
for outputting an internal power supply potential VBB according to the reference potential Vref
2
, and a pad
556
connected to a node receiving the internal power supply potential VBB, for observing a potential.
The internal power supply potential Vccp is a power supply potential for peripheral circuitry that is supplied to an input/output (I/O) buffer of the DRAM, and the like. The internal power supply potential Vcca is a power supply potential that is supplied to a memory array and the like. The internal power supply potential VPP is a boosted potential for activating a word line of the memory array and the like. The internal power supply potential VBB is a negative potential that is supplied to the well where the memory array is formed, and the like.
FIG. 23
is a circuit diagram showing the structure of the constant current control circuit
542
of FIG.
22
.
Referring to
FIG. 23
, the constant current control circuit
542
includes a resistance
572
connected between a node receiving an external power supply potential Vcc and a node N
51
, a P-channel MOS transistor
574
having its source connected to the node N
51
and its gate and drain connected to a node N
52
, an N-channel MOS transistor
576
connected between the node N
52
and a ground node and having its gate connected to a node N
54
, an N-channel MOS transistor
582
having its gate and drain connected to the node N
54
and its source connected to the ground node, a P-channel MOS transistor
580
connected between a node N
53
and the node N
54
and having its gate connected to the node N
52
, and a resistance group
578
connected between the node receiving the power supply potential Vcc and the node N
53
. The potentials V
2
, Viconst and Vbias are output from the nodes N
51
, N
52
and N
54
, respectively.
The resistance group
578
includes resistances
586
.
1
to
586
.k connected in series between the node receiving the power supply potential Vcc and the node N
53
.
FIG. 24
is a diagram showing output potential characteristics of the constant current control circuit
542
of FIG.
23
.
Referring to
FIGS. 23 and 24
, after the external power supply potential Vcc exceeds a threshold voltage|Vtp| of the P-channel MOS transistor, the potential Viconst rises with increase in power supply potential Vcc.
On the other hand, the potential Vbias rises with increase in power supply potential Vcc until the power supply potential Vcc reaches a threshold voltage Vtn of the N-channel MOS transistor. However, the potential Vbias becomes approximately constant after the power supply potential Vcc exceeds the threshold voltage Vtn.
FIG. 25
is a circuit diagram showing the structure of the reference potential generating circuit
544
of FIG.
22
.
Referring to
FIG. 25
, the reference potential generating circuit
544
includes a P-channel MOS transistor
592
connected between a node receiving the potential V
2
and a node N
61
and receiving the potential Viconst at its gate, and a resistance circuit
594
connected between the node N
61
and the ground node. The reference potential Vrefp is output from the node N
61
.
The resistance circuit
594
includes P-channel MOS transistors
596
.
1
to
596
.j connected in series between the node N
61
and the ground node and having their gates connected to the ground node, and fuse circuits
598
.
1
to
598
.j connected in parallel with the P-channel MOS transistors
596
.
1
to
596
.j, respectively.
The P-channel MOS transistor
592
, which receives the potential Viconst at its gate, serves as a constant current source. Thus, a constant current flows into the resistance circuit
594
, and the reference potential Vrefp is output according to the resistance value of the resistance circuit
594
. This reference potential Vrefp is constant even if the external power supply potential Vcc varies.
The Vccp generating circuit
546
of
FIG. 22
generates the internal power supply potential Vccp for output, based on the reference potential Vrefp thus stabilized at a constant value.
FIG. 26
is a circuit diagram showing the structure of the fuse circuit
598
used in FIG.
25
.
Referring to
FIG. 26
, the fuse circuit
598
includes a fuse element
600
connected between nodes N
62
and N
63
, and an N-channel MOS transistor
602
connected between the node N
63
and a node N
64
and having its gate connected to a pad
604
. The fuse circuits
598
.
1
to
598
.j of
FIG. 25
have the same structure as that of the fuse circuit
598
of FIG.
26
.
Conventionally, an internal power supply potential in the DRAM is adjusted during wafer testing.
More specifically, the fuse circuits
598
.
1
to
598
.j of
FIG. 25
are switched between conductive and non-conductive states by a test signal supplied from the respective pads
604
of
FIG. 26
, in order to vary the reference potential Vrefp. Then, the internal power supply potential Vccp is observed with the pad
548
of
FIG. 22
, and a fuse element
600
is blown according to the test signal that corresponds to an optimal internal power supply potential Vccp. The fuse element
600
is blown with laser beams.
For example, however, in the case where the transistor threshold voltage Vth becomes lower than the assumed value due to variation in process up to the wafer testing, there may be a lot including
McDermott & Will & Emery
Mitsubish Denki Kabushiki Kaisha
Zweizig Jeffrey
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