Semiconductor device manufacturing: process – Forming schottky junction – Using refractory group metal
Reexamination Certificate
2000-08-17
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming schottky junction
Using refractory group metal
C438S674000
Reexamination Certificate
active
06391750
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and manufacturing processes, and more particularly to methods for differentially forming various contact resistance in semiconductor devices comprising high density metal'oxide semiconductor field effect transistor (MOSFET) devices.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronic industry has undergone a revolution by the use of semiconductor technology to fabricate small and highly'integrated electronic devices. A large variety of semiconductor devices have been manufactured with various applications in numerous disciplines. Presently, the most common and important semiconductor technology is based on silicon, and one such silicon-based semiconductor devices is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
The principle elements of a typical MOSFET device comprise, as shown in
FIGS. 1A and 1B
, a semiconductor substrate
10
, typically lightly doped monocrystalline silicon. A gate electrode
16
, typically a heavily doped conductor, is disposed on the substrate
10
and a gate input signal is applied to the gate electrode
16
via a gate terminal
28
in
FIG. 1B. A
channel region
15
is formed in the substrate
10
below the gate electrode
16
. Heavily doped active regions
18
, i.e., source and drain regions, are formed at both sides of the channel region
15
within the substrate
10
. The gate electrode
16
is separated from the substrate
10
by a gate insulation layer
14
to prevent current from flowing between the gate electrode
16
and the source and drain regions
18
or the channel region
15
. Sidewall spacers
20
are disposed on the side surfaces of the gate electrode
16
. Dielectric insulators
12
are locally provided to electrically isolate one transistor from another. Various horizontal conductive lines
24
are formed over the substrate, electrically contacting the active regions
18
or gate electrodes
16
of the transistors and devices for intra-layer interconnection. An interlayer dielectric
26
is provided over the substrate
10
, covering the elements described above, and through the openings formed in the interlayer dielectric
26
, vertical conductive lines
28
are formed to provide conductive paths among the transistors and devices in different layers for inter-layer interconnection.
As transistor dimensions approached one micron in diameter, conventional parameters resulted in intolerable increased resistance between the active region
18
and the conductive lines
24
,
28
. The principle way of reducing such contact resistance is by formation of a metal silicide
22
atop the active regions
18
and gate electrodes
16
prior to application of the conductive film for formation of the various conductive lines
24
,
28
. One common metal silicide material is TiSi
2
. The TiSi
2
material is typically provided by first applying a thin layer of titanium atop the wafer which contacts the active regions. Then, the wafer is subjected to one or more high temperature annealing steps. This causes the titanium to react with the silicon of the active regions and gate electrodes, thereby forming TiSi
2
. Such a process is referred to as a salicide (self-aligned silicide) process because the TiSi
2
is formed only where the titanium material contacts the silicon active regions and polycrystalline silicon gate electrodes.
As device dimensions continue to shrink, thicker silicide layers are required to reduce the contact resistance. Conventionally, silicide has been formed with a uniform thickness over the entire active regions on a single chip, without considering each individual transistor's influence on the overall chip speed. In such cases, failure to provide a sufficient amount of silicide on the active regions causes degradation of overall chip speed. In addition, the uniform thickness silicide formation results in forming an excessive amount of silicide on the active regions that have less influence on the overall chip speed, thereby increasing the manufacturing costs.
Thus, there is a continuing need for improved methods and structures that enable the selective formation of various contact resistances depending on each device's criticality and influence on the overall chip speed performance.
SUMMARY OF THE INVENTION
The present invention provides methods and structures that increase the overall chip speed performance and reduces the manufacturing costs during the formation of both intra-layer and inter-layer interconnects by selectively providing various contact resistances based on each individual transistor's influence on overall chip speed.
Thus, in accordance with one aspect of the present invention, there is provided a method for selectively controlling contact resistance in semiconductor devices. The method includes forming first silicide layers having a first thickness on first active regions having a first impurity concentration in a first device region, and forming second silicide layers having a second thickness greater than the first thickness on second active regions having a second impurity concentration smaller than the first impurity concentration in a second device region.
Thus, in accordance with one aspect of the present invention, there is provided a method for selectively controlling contact resistance in semiconductor devices. The method includes forming first silicide layers having a first thickness on first active regions having a first impurity concentration in a first device region, and forming second silicide layers having a second thickness greater than the first thickness on second active regions having a second impurity concentration smaller than the first impurity concentration in a second device region.
In accordance with another aspect of the present invention, there is provided a another method for selectively controlling contact resistance in a semiconductor device. The method includes forming first active regions having a first impurity concentration within a first device region and second active regions having a second impurity concentration smaller than the first impurity concentration within a second device region; and forming silicide on the first and second active regions.
In accordance with a still further aspect of the present invention, there is provided a semiconductor device structure which comprises a first device region and a second device region. The first device region comprises first active regions having a first impurity concentration and first silicide layers formed on the first active regions and having a first thickness. The second device region comprises second active regions having a second impurity concentration smaller than the first impurity concentration and second silicide layers formed on the second active regions and having a second thickness greater than the first thickness.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5034348 (1991-07-01), Hartswick et al.
patent: 5610088 (1997-03-01), Chang et al.
patent: 5654212 (1997-08-01), Jang
patent: 5953612 (1999-09-01), Lin et al.
patent: 6040606 (2000-03-01), Blair
patent: 6103610 (2000-08-01), Blair
patent: 6235568 (2001-05-01), Murthy et al.
Besser Paul R.
Chen Susan H.
Advanced Micro Devices , Inc.
Le Bau T
Nelms David
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