Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-06-07
2002-01-08
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
Reexamination Certificate
active
06337650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and a method for regenerating a stable clock signal for a semi-synchronization type digital demodulating apparatus used in satellite communication, and more particularly to the system and the method for regenerating the stable clock signal with a reduced jitter component.
2. Description of the Related Art
There have conventionally been proposed the above-mentioned type of various clock-signal regenerating systems for use in a semi-synchronization type digital demodulating apparatus. Of these, such a system is known that over-samples a change point in demodulated analog data using an analog/digital (A/D) converter and then adjusts that data's sampling timing using a PLL (Phase Lock Loop).
Note here that throughout the following drawings, same components are indicated by same reference symbols and numerals. As shown in
FIG. 3
, at an input terminal
1
to which is input an demodulated analog data signal with a symbol frequency Fs, an A/D converter
2
is connected, which converts the demodulated analog data signal into a digital signal.
To the A/D converter
2
is connected a voltage-controlled oscillator (VCXO)
8
, which outputs a clock signal
12
having a sampling frequency (2* Fs) twice as high as the symbol frequency (Fs) to the A/D converter
2
.
The A/D converter
2
is in turn connected to a data-change-direction detecting circuit
3
, which receives a most significant bit (MSB) converted at the AID converter
2
to detect a data-change direction of the above-mentioned demodulated analog data and then output a data-change-direction signal
13
. Since information of the data-change direction is enough to tell whether the demodulated analog data changed from +1→−1 or −1→+1 in direction, not all bits but only a most significant bit is required to make a decision of that direction.
The A/D converter
2
is also connected to a phase-difference detecting circuit
4
, which detects a phase difference between a clock signal
12
of the voltage-controlled oscillator
8
and demodulated analog data at the input terminal
1
, and outputs a phase-difference signal
14
.
To the data-change-direction detecting circuit
3
and the phase-difference detecting circuit
4
is connected a multiplier (XOR)
5
, which multiplies the phase-difference signal
14
from the phase-difference detecting circuit
4
by the data-change-direction signal
13
from the data-change-direction detecting circuit
3
, and outputs a resultant phase-difference signal including information of phase lag and lead.
To the multiplier
5
is connected a digital/analog (D/A) converter
6
, which converts a digital output signal from the multiplier
5
into an analog signal.
To the D/A converter
6
is connected a low-pass filter (LPF)
7
, which removes a high-frequency component from an output signal of the D/A converter
6
and outputs the resultant phase control signal to the voltage-controlled oscillator
8
, to control the voltage-controlled oscillator
8
so as to synchronize in phase the above-mentioned demodulated analog data with the clock signal
12
.
To the voltage-controlled oscillator
8
is connected a frequency divider
9
, which divides to ½ the frequency of a signal obtained by thus phase-synchronizing the above-mentioned demodulated analog data and the clock signal
12
and then output thus regenerated clock signal at an output terminal
10
.
As shown at the upper part of
FIG. 4
, the demodulated analog data is input at the input terminal
1
, to form an eye pattern which is the analog signal with the frequency Fs and also which changes in amplitude between two peak positions of “+1” and “−1.”
As shown at a lower part of the
FIG. 3
, the clock signal
12
sent from the voltage-controlled oscillator
8
to the A/D converter
2
has, as mentioned above, a sampling frequency of 2* Fs, so that double over-sampling is performed at the A/D converter
2
.
At the A/D converter
2
, as shown in the
FIG. 3
, data is sampled at two points, on a rising edge of the clock signal
12
, of one data convergence point of timing A and an other data convergence point (zero-crossing point) of timing B. That is, the timing A is a peak position of the demodulated analog data and the timing B, the zero-crossing point thereof.
Next, an example of operations of the data-change-direction detecting circuit
3
is explained as follows. The data-change-direction detecting circuit
3
uses only the MSB of the demodulated analog data sampled by the A/D converter
2
and also the data present at the sampling timing A shown in
FIG. 4
, to detect the data-change direction.
That is, although the MSBs of the demodulated analog data sampled at the timing points A and B shown in
FIG. 4
are input to the data-change-direction detecting circuit
3
, it can detect the data-change direction using only the demodulated analog data that was sampled at the timing A.
Since a center voltage (DC offset voltage) of the demodulated analog data input to the A/D converter
2
is aligned with a center of an input range for the A/D converter
2
, peak positions “+1” and “−1” of the demodulated analog data can be decided using only the MSB of the data sampled at the timing A.
The data-change-direction detecting circuit
3
uses two consecutive data pieces sampled at the timing A shown in
FIG. 4
, to detect a change in the peak position of the demodulated analog data from “+1” to “−1” or vice versa. For example, the data-change-direction detecting data-change-direction detecting circuit
3
compares the MSB of the data sampled at t=1 to that at t=3, then that at t=3 to that at t=5, and then that at t=5 to that at t=7, and so on, respectively.
When the data-change-direction detecting circuit
3
decides, based on this comparison, that the demodulated analog data changed from its peak positions of “−1” to “+1,” it outputs “+1” as the data-change direction signal
13
. When the data-change-direction detecting circuit
3
decides a change of the demodulated analog data from its peak positions “+1” to “−1,” it outputs “−1” as the data-change direction signal
13
.
If the demodulated analog data stays unchanged, for example, as from “−1” to “−1” or from “+1” to “+1,” the data-change-direction detecting circuit
3
outputs “0” as the data-change-direction signal
13
.
Next, an example of operations of the phase-difference detecting circuit
4
is described as follows. The phase-difference detecting circuit
4
in turn receives demodulated analog data sampled at the timing points A and B, of which the data sampled at the timing B is used to detect the phase difference between the clock signal
12
and the demodulated analog data as follows.
When, as shown in
FIG. 5A
, demodulated analog data is changed in its peak position from “−1” to “+1,” changes in the demodulated analog data of waveforms (
24
-
1
), (
24
-
2
), and (
24
-
3
) indicate a state where phase synchronization is established between the clock signal
12
and the demodulated analog data, while changes of the demodulated analog data of waveforms (
24
-
4
) and (
24
-
5
) indicate the state where that synchronization is not established therebetween.
Likewise, as shown in
FIG. 5B
, when demodulated analog data changed in its peak position from “+1” to “−1,” changes in the demodulated analog data of waveforms (
25
-
1
), (
25
-
2
), and (
25
-
3
) indicate the state where phase synchronization is established between the clock signal
12
and the demodulated analog data, while changes in the demodulated analog data of waveforms (
25
-
4
) and (
25
-
5
) indicate the state where synchronization is not established therebetween.
As shown in
FIG. 5A
, the prior-art phase-difference detecting circuit
4
detects, with respect to the zero-crossing position, the phase difference of ±&Dgr;V
1
for the change
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