Internal address generator of semiconductor memory device

Details Internal address generator of semiconductor memory device Internal address generator of semiconductor memory device

1996-12-27

1998-07-28

Fears, Terrell W.

Static information storage and retrieval

Addressing

36523006, G11C 1300

Patent

active

057870454

ABSTRACT:
An internal address generator of a semiconductor memory device which can achieve a high speed operation. The internal address generator includes at least two bit counters which input a less significant AND-SUM signal from a less significant bit counter and each input an external address signal of 2 bits or more by 1 bit, commonly responding to an enable signal and a clock signal, each bit counter having: a first pass transistor connected between an output terminal and a first node and being responsive to the clock signal; a first inverter for inverting a logic value from the output terminal; a second pass transistor for transmitting an output signal from the first inverter to the first node; second and third inverters parallel-coupled between the first node and a second node to form a feedback loop; fourth and fifth inverters parallel-coupled between third and fourth nodes to form a feedback loop; a third pass transistor connected between the second and third nodes; a sixth inverter connected between the fourth node and the output terminal; a clock switching part for transmitting the clock signal to the third pass transistor during a counter mode in accordance with logic values of the enable signal and the less significant AND-SUM signal; an address switching part for selectively transmitting an external address signal to the third node in accordance with the logic value of the enable signal; a loop switching part for applying the clock signal to the first pass transistor to drive the first pass transistor complementarily to the third pass transistor, during the count mode and to complementarily drive the first and second pass transistors, during a loading mode, in response to the logic values of the enable signal and the less significant AND-SUM signal; and an AND-SUM operation part for generating an AND-SUM signal by a logic signal on the third node and the less significant AND-SUM signal.

REFERENCES:
patent: 5274594 (1993-12-01), Yanagisawa et al.
patent: 5392252 (1995-02-01), Rimpo et al.
patent: 5430686 (1995-07-01), Tokami et al.

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