Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reissue Patent
1996-11-20
2002-01-08
Karlsen, Ernest F. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S073100, C714S733000
Reissue Patent
active
RE037500
ABSTRACT:
The present invention relates to testing of integrated circuits by partitioning the integrated circuit into submodules by the use of three-way analog switches, and individually testing the partitioned submodules. Specifically, a technique which reduces the number of required transmission gates, while increasing the level of testability is described.
The design of integrated circuits generally consists of multiple subcircuits, referred to hereinafter as submodules, which are interconnected to form an overall module circuit. After fabrication, each module circuit is tested prior to shipment in a variety of ways to establish that it is operating properly.
The module may be tested as a single entity by placing known electrical signals on the module circuit input ports while observing output phenomena on the output ports. The disadvantage in testing the module device from external input and output ports results because the number of test cases required grows exponentially with the complexity of the module. Signal masking effects make it difficult to exercise all submodules, and the settling time varies greatly between submodules. This is especially significant for analog circuits.
Various techniques have been proposed to employ a “divide and conquer” strategy by partitioning the module into submodules in order that each submodule may be effectively isolated from the other submodules, and tested in its isolated condition to determine that each submodule works correctly.
Circuit techniques are employed on the individual module for gaining access to the internal ports of each submodule which has no direct connection to any external I/O pad of the module.
These techniques have been employed for digital and analog circuit modules, as well as for modules which are mixed analog digital circuits. One such technique, is described in an article entitled “Design for Testability for Mixed Analog/Digital ASICS” IEEE, 1988, Custom Integrated Circuits Conference, pages 16.5.1-16.5.4. This technique divides a mixed analog/digital ASIC chip into analog blocks and digital blocks, and uses multiplexers connected to internal ports between the blocks, permitting that internal port to be either controlled or observed from external I/O pads, depending on test mode control signals applied to the multiplexers.
In a paper entitled “Design for Testability of Mixed Signal Integrated Circuits” by Kenneth Wagner and T. W. Williams, 1988 International Test Conference, paper 39.1 pages 823-828, there is described a technique for providing macrotests on an integrated circuit. The circuit module is partitioned into a number of submodules, or macros, which define their own specific function.
In carrying out the partitioning of the circuit module, analog macro inputs are isolated and controlled so that macro outputs may be observed, via the use of analog multiplexers. The use of multiplexers requires an undesirable amount of module layout area overhead, as well as the necessity of running numerous additional wires from the multiplexer to various internal ports. There is also a limitation on the number of test configurations which may be conducted.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a system for partitioning a circuit module into individual testable submodules.
It is a more specific object of this invention to partition a circuit module using a minimum number of switching elements to preserve layout area.
It is yet another object of this invention to provide for a system for dynamically partitioning submodules within a circuit module in accordance with the sequence of data input to the device.
These and other objects of the invention are provided by extra circuitry added to the circuit module which will partition the module into individual submodules. In carrying out the invention, analog switches consisting of transmission gates are used to access the normal signal paths between submodules. The transmission gates are advantageously located near an internal input port of a submodule in the path of a signal line connecting the internal port to another internal output port of a second submodule. The transmission gates are additionally connected to a conductor of a test bus.
Each of the submodules having ports which are to be asserted or observed are connected through a transmission gate to the adjacent submodule. A logic circuit is provided for setting the switch state so that identified internal ports are either connected to a test bus conductor, which will supply an asserted condition to the input port, or the conductor is connected to the input port without disturbing the normal paths through the module, permitting observation of the signal conditions on the input port.
Extra input/output paths may be added to the module circuit substrate to accommodate shifting in data to the logic circuit, as well as provide direct access to one of the test bus conductors.
REFERENCES:
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patent: 1492219 (1924-04-01), Quass
patent: 1533153 (1925-04-01), Williams, Jr.
patent: 4286173 (1981-08-01), Oka et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4743841 (1988-05-01), Takeuchi
patent: 4893311 (1990-01-01), Hunter et al.
patent: 4918379 (1990-04-01), Jongepier
McClusky, E.J., “Design . . . ”; IEEE Trans. on Computers; v. C-30; No. 11; Nov. 1981; pp. 866-874.*
Wagner et al; “Design for Testability . . . ”; IEEE 1988 Internat. Test Conference, Paper 39.1; 1988; pp. 823-828.*
Fasang et al; “Design for Testability . . . ”; Proceedings of the IEEE 1988 Custom Integrated Circuits Conference; pp. 16.5.1-16.5.4.
Karlsen Ernest F.
Marion Michael E.
North American Philips Corporation
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