Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-08-17
2002-05-07
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S713000, C438S714000
Reexamination Certificate
active
06383939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements associated with a multi-purpose graded silicon oxynitride cap layer in non-volatile memory semiconductor devices.
2.Background Art
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell
8
is depicted in
FIG. 1A
, viewed in a cross-section through the bit line. Memory cell
8
includes a doped substrate
12
having a top surface
11
, and a source
13
a
and a drain
13
b
formed by selectively doping regions of substrate
12
. A tunnel oxide
15
separates a floating gate
16
from substrate
12
. An interpoly dielectric
24
separates floating gate
16
from a control gate
26
. Floating gate
16
and control gate
26
are each electrically conductive and typically formed of polysilicon.
On top of control gate
26
is a silicide layer
28
, which acts to increase the electrical conductivity of control gate
26
. Silicide layer
28
is typically a tungsten silicide (e.g., WSi
2
), that is formed on top of control gate
26
prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell
8
can be programmed, for example, by applying an appropriate programming voltage to control gate
26
. Similarly, memory cell
8
can be erased, for example, by applying an appropriate erasure voltage to source
13
a.
When programmed, floating gate
16
will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate
16
can be programmed to a binary 1 by applying a programming voltage to control gate
26
, which causes an electrical charge to build up on floating gate
16
. If floating gate
16
does not contain a threshold level of electrical charge, then floating gate
16
represents a binary 0. During erasure, the charge is removed from floating gate
16
by way of the erasure voltage applied to source
13
a.
FIG. 1B
depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG.
1
A). In
FIG. 1B
, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate
12
. For example,
FIG. 1B
shows a portion of a floating gate
16
a
associated with a first memory cell, a floating gate
16
b
associated with a second memory cell, and a floating gate
16
c
associated with a third memory cell. Floating gate
16
a
is physically separated and electrically isolated from floating gate
16
b
by a field oxide (FOX)
14
a.
Floating gate
16
b
is separated from floating gate
16
c
by a field oxide
14
b.
Floating gates
16
a,
16
b,
and
16
c
are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate
12
, tunnel oxide
15
, and field oxides
14
a
and
14
b.
Interpoly dielectric layer
24
has been conformally deposited over the exposed portions of floating gates
16
a,
16
b,
and
16
c
and field oxides
14
a
and
14
b.
Interpoly dielectric layer
24
isolates floating gates
16
a,
16
b
and
16
c
from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate
26
. Interpoly dielectric layer
24
typically includes a plurality of films, such as, for example, a bottom film of silicon, dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of memory cells, and in particular the basic functions depicted in the memory cells of
FIGS. 1A and 1B
, places a substantial burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate-control gate structure, without causing adverse effects within the resulting memory cells. Of particular concern, is the limited resolution encountered during photolithography. In particular, the memory gate stack, illustrated in
FIG. 1A
, uses conventional photolithography techniques that typically require a resist thickness of typically 8,000 to 9,000 Angstroms. In addition, the thickness of the resist mask is reduced during etching of the layer stack including layers
28
,
26
,
24
, and
16
. Hence, the relatively thick layer of photoresist is necessary in order to ensure that the resist mask pattern is preserved during etching of the layer stack.
Use of a mask pattern having a resist thickness of 8,000 to 9,000 Angstroms, however, substantially limits the resolution of the conventional deep ultraviolet (DUV) lithography techniques. Specifically, although DUV lithography may be used to form a gate having a width of around 0.25 microns, the depth of the resist of about 8,000 to 9,000 Angstroms limits the depth of field resolution during resist patterning, such that the spaces between the resist line are a minimum width of about 0.3 microns. Hence, the ability to increase the density of memory cells in a memory array by reducing the spacing between memory gates is limited by conventional DUV photolithography techniques.
SUMMARY OF THE INVENTION
There is a need for increasing the density of a memory gate structure in a deep submicron memory core using conventional DUV lithography techniques.
There is also a need for an arrangement for reducing the spacing in resist mask patterns used to form memory gate structures by reducing the mask thickness, without loss of the mask pattern during etching of the memory gate stack.
These and other needs are attained by the present invention, where a resist mask is formed on an antireflective coating layer and has a resist thickness sufficient to withstand removal during etching of the antireflective coating layer. The antireflective coating layer has a sufficient thickness to include a sacrificial thickness portion, sufficient to withstand removal during etching of the stacked layers on the semiconductor wafer, and also including a stop-layer thickness sufficient for memory gate spacer formation. The increase in thickness of the antireflective coating layer to include a sacrificial thickness enables formation of a resist mask to have a thickness sufficient to withstand removal during etching of the deposited antireflective coating layer. Once the antireflective coating layer has been etched based on the resist mask, the etched antireflective coating layer may be used as a mask for self-aligned etching of the remaining layers. Moreover, addition of the sacrificial thickness in the antireflective coating layer enables the antireflective coating layer to have a sufficient stop-layer thickness, following etching, sufficient for memory gate spacer formation during subsequent processing.
According to one aspe
Shen Lewis
Yang Wenge
Advanced Micro Devices , Inc.
Hiteshew Felisa
Vinh Lan
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