Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-08-26
2002-04-02
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C438S427000, C438S435000
Reexamination Certificate
active
06365952
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to isolating devices on an integrated circuit, and more specifically to isolating the devices with isolation trenches.
BACKGROUND OF THE INVENTION
Integrated circuits are often fabricated with multiple devices, such as transistors. To minimize integrated circuit size, and hence integrated circuit cost, these devices are often positioned in close proximity to one another. As a result, undesirable inter-device effects can arise. For example, undesired current can leak between devices. Alternatively, a device such as a transistor can switch on as a result of positive feedback between proximate devices. This effect is known as latch-up. Leakage current and latch-up are understood by persons skilled in the art.
To diminish these unwanted inter-device effects, it is desirable to adequately isolate proximate devices. Conventionally, inter-device isolation is accomplished by creating a field oxide between the devices. The field oxide is an electrical insulator. Thus, proximate devices are substantially electrically isolated if the field oxide has adequate dimensions including height, length, and width. However, if the field oxide dimensions are too small, leakage current and latch-up may result.
For example, the undesired inter-device effects may arise if a parasitic metal-oxide-semiconductor field effect transistor (MOSFET) is created between two adjacent devices.
FIG. 1
illustrates one embodiment of a parasitic MOSFET
10
on an integrated circuit formed by a conductor
12
, active areas
14
, and a field oxide
16
. The integrated circuit may be a memory, which contains memory cells and complementary MOSFETS. The active areas may be the source and the drain of memory cells or MOSFETs. The conductor
12
may be a wordline of the flash memory. The design and operation of flash memory are known by persons skilled in the art.
The structure of the parasitic MOSFET
10
is now described. The parasitic MOSFET
10
is unintentionally formed by elements of surrounding devices. The conductor
12
and the field oxide
16
function as a gate of the parasitic MOSFET
10
. The active areas
14
serve as the source and drain of the parasitic MOSFET
10
. Although it is not constructed like a conventional transistor, the parasitic MOSFET
10
, nevertheless, may function like one if the field oxide
16
has sufficiently small dimensions. As a result, operation of the parasitic MOSFET
10
may cause undesirable leakage current and latch-up in surrounding devices. Therefore, it is necessary to maintain adequate field oxide
16
dimensions.
Methods of improving device isolation by enhancing field oxide
16
dimensions have been previously disclosed. U.S. Pat. Nos. 5,358,894 and 5,438,016 teach processes for reducing the thinning of the field oxide
16
thickness by respectively applying an impurity and using protective structures. However, these patents do not recite methods or structures that increase the depth that the field oxide
16
penetrates the substrate
18
, while keeping the lateral encroachment to a minimum to maximize the area available for device fabrication. Many of these approaches also require multiple masking steps which increase processing costs. A process that minimizes the number of processing steps or masking steps is highly desirable.
In ULSI, devices will be positioned in closer proximity to one another than is done in very large scale integrated circuits (VLSI). However, with current technology, the field oxide
16
may be insufficiently deep, or in other words, does not penetrate sufficiently far into the substrate
18
, to isolate the devices. Thus, undesirable leakage current and latch-up may occur in the devices. Therefore, a process and structure for isolating high density devices is necessary.
Furthermore, integrated circuits are fabricated with devices having microscopic, such as sub-micron, features that can only be manufactured with critical processing steps. The critical processing steps entail carefully aligning the substrate
18
to equipment used to build the devices. This requires that most processes leave the substrate
18
in a relatively planar configuration. Therefore, an integrated circuit fabrication process that is less sensitive to process variations is desirable. Such a process would permit successful fabrication of integrated circuits, despite minor misalignments.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided an isolation trench in an integrated circuit, and a method of forming the same using self-aligned processing techniques. The isolation trench is created by first forming a shallow trench defined by a mask. The shallow trench is filled with an insulator, such as an oxide. Then some of the insulator is removed. Next, a deep trench is formed in self alignment between the remaining insulator.
In one embodiment, a second oxide is then formed on the integrated circuit. The second oxide is later removed from the shallow trench. Polysilicon is then deposited in the shallow trench. The polysilicon is oxidized and annealed to form field oxide. As a result, the present invention, particularly the deep trench, facilitates enhanced inter-device isolation in high density integrated circuits. Hence, unwanted inter-device effects, such as leakage current and latch-up, are diminished while creating minimal variations in topography. This is desirable for device processing.
In another embodiment, nitride is formed on the walls of the shallow trench. As a result, the field oxide will not significantly encroach neighboring active areas. Reduced encroachment increases the amount of area available for fabrication of devices.
It is also a feature of the present invention that the field oxide may be formed on the integrated circuit with a flat topography without using planarization techniques, such as chemical-mechanical processing or resist etchback. Furthermore, it is an advantage of the present invention that ion implantation is not required to provide inter-device isolation.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
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Chaudhuri Olik
Duy Mai Anh
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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