Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-02-15
2002-05-28
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
27, 27
Reexamination Certificate
active
06396138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to semiconductor chip packages and, in particular, to improving the heat dissipation of such chip packages.
2. Related Art
With reference to
FIG. 1
, a semiconductor package
10
according to the prior art is shown. The semiconductor package
10
includes a bottom plate portion
13
(such as lead frame segment) and terminals
12
a
,
12
b
. A semiconductor die
16
is disposed on top of the bottom plate portion
13
and fastened thereto, typically using a conductive epoxy material
14
. The semiconductor die
16
includes a metalized region
18
defining a connection area for a top surface of the semiconductor die
16
. An array of semiconductor diffusions (not shown) lie below metalized region in die
16
. Portions of the terminals
12
a
,
12
b
, bottom plate portion
13
(which may be parts of a common lead frame, and semiconductor die
16
are encapsulated in a housing
22
, typically formed from a moldable material in a transfer molded operation. In order to obtain an electrical connection between the metalized region
18
and the terminal(s)
12
b
, one or more conductive wires
20
are ultrasonically bonded at one end
21
a
to the metalized region
18
and at a distal end
21
b
to the terminal
12
b.
FIG. 2
shows another semiconductor package
100
of the prior art. In order to electrically connect the metalized region
18
with the terminal
12
b
, one or more wires
24
are stitch bonded at locations
23
, thereby providing additional paths for current to flow from the semiconductor die
16
to the terminal
12
b
. This reduces the resistance of the current path from the semiconductor die
16
to the terminal
12
b.
The devices described above have a number of disadvantages. The devices can exhibit higher resistance and inductance in the current paths through the package than is acceptable. High resistance and inductance can significantly and deleteriously impact the high frequency performance of certain semiconductor devices, such as MOSFETs.
Referring to
FIG. 1
, for example, it is seen that much of the upper metalized surface
18
is relatively remote from the bond
21
a
with wire
20
(such as the portion at the distance “D”). Thus, the current path for the source connections (in the case of a MOSFET) of the semiconductor junctions in the central region of the die
12
must pass a significant distance through the thin metalized contact layer
18
. Although additional wire connections could be provided to the other regions, including, for example, by the stitch bonding of
FIG. 2
, construction of such a device is more complex and costly than for the device of FIG.
1
.
In addition, the wire(s)
20
themselves introduce significant resistance and inductance in the current path between the terminal
12
b
and the metal contact layer
18
. While the number of wire bonds could be increased, construction of such a device is again complex and costly.
The heat generated by the devices of
FIGS. 1 and 2
can also create problems in performance. As noted above, an array of semiconductor elements, comprising p-n junction regions, lies below the surface of metalized region
18
. There can be thousands of semiconductor elements on a typical cellular type MOSgated device die. Thus, the heat generated by electrical conduction through the die is significant and is concentrated at the upper surface, adjacent the thin metalized layer
18
. The thin metalized region
18
cannot provide significant heat dissipation; nor can the thicker bottom plate
13
, since it is removed to the opposite side of the silicon die
12
. Such heat generation within the device increases resistances and inductances, again degrading performance.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor package having decreased electrical resistance to the upper die junction patterns of the semiconductor elements residing therein, as well as improved heat dissipation of the semiconductor elements. By “upper die junction patterns”, it is meant the electrical connections made between the top metal surface layer of the package and the semiconductor elements residing therein. (These will also be referred to as the “upper die connections”.) For example, for a MOSFET, it may refer to the source connections of the semiconductor elements; for an IGBT or other transistor, it may refer to the emitter; for a diode it may be the anode, etc.
In accordance with the present invention, a conforming metal layer extends between the metalized region exposed on the top surface of the die (connected with the upper die connections of the semiconductor elements) and lands or other conductive areas on the upper surface of the substrate used for providing an external electrical source connection. The conforming metal layer provides a substantial low resistance electrical pathway between all portions of the metalized region and the lands, thus reducing the electrical resistance to the semiconductor elements. The conforming metal layer is relatively thick and is in direct contact with much of the metalized region, thus also providing substantial heat dissipation of the semiconductor elements.
Thus, in general, the present invention provides a semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.
The invention also includes a semiconductor device comprising a substrate having an upper surface with a central region and a surrounding perimeter region. The surrounding perimeter region has at least one electrical land residing thereon. A die having a bottom surface portion is supported by at least a portion of the central region of the substrate and includes a top surface portion comprising a metal layer and a number of junctions of semiconductor elements below the metal layer. The top surface portion and the bottom surface portion of the die are separated by a die body portion lying above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical land on the perimeter region of the substrate.
The invention includes a method of manufacturing conforming metal layers for semiconductor packages or die arrayed on the surface of a wafer. First, an insulating layer is applied to any exposed areas on the upper surface of each package that are electrically connected to the semiconductor elements other than the upper die connections of the semiconductor elements. (Thus, for example, any exposed connections with the drain or gates of MOSFET semiconductor elements on the upper surface would be so insulated.) Any electrical connections on the upper surface of the substrate (such as lands) that are to electrically interface with the upper metalized region remain significantly exposed.
A dam is fabricated surrounding the perimeter of the wafer, thus enveloping all die thereon. The dam extends higher than the highest point of each die, including any insulation. A flowable, curable metal is poured into the top portion of the wafer defined by the conductive dam. The flowable metal is sometimes termed a “lead free replacement” metal. Other materials, for example, a conductive epoxy could also be used as the “flowable metal”. The flowable metal fills in all of the contours exposed on the upper surfaces of eac
Chaudhuri Olik
Ha Nathan W.
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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