Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
1999-12-30
2002-07-23
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S589000, C330S009000
Reexamination Certificate
active
06424208
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to low voltage op-amp circuits that utilize one or more metal oxide semiconductor field effect (MOSFET) shunt switches to couple key circuit nodes together. More particularly, the present invention relates to the design of low voltage operational amplifier circuits with switched capacitor elements.
BACKGROUND OF THE INVENTION
A variety of desirable complimentary metal oxide semiconductor (CMOS) operational amplifier (“op-amp”) circuits are well-known in the field of analog and digital circuit design. These include a variety of CMOS op-amp circuits with switching elements composed of metal oxide semiconductor field effect transistors (MOSFETs). There are many applications where the switching elements are operated in either an “on” or “off” mode to regulate or control other circuit elements. In addition to digital circuit applications, a variety of op-amp circuits incorporate a plurality of switching elements. In the context of operational amplifier circuits, MOSFET switches are used, for example, to couple other impedance elements (e.g., capacitors) to input or feedback paths of an op-amp. MOSFET switches are also used to perform a reset function in op-amp circuits.
At typically power supply voltages of three-to-five volts, MOSFET switches can be modeled as having a sufficiently low enough on-resistance that their non-ideality can be ignored in analyzing the operation of many circuits. An ideal switch has a infinite conductance (zero resistance) in its on-state and zero conductance (infinite resistance) in its off-state. At conventional power supply voltages MOSFET switching elements are often modeled as performing a shunt-switch function because the MOSFET switch has a resistive impedance that is sufficiently small that a negligible voltage drop occurs across the switch.
The design of CMOS op-amp circuits that operate at a low power supply voltage presents special design problems. Low voltage CMOS circuit design is generally considered to include CMOS circuits operating at a supply voltage below about three volts, corresponding to the power supply voltage of current high performance microprocessors. Some consumer electronic devices currently operate at even lower power supply voltages. Miniature hearing aids, in particular, typically have a power supply comprising a single miniature battery with a nominal voltage of about 1.5 volts, corresponding to the voltage of a single miniature electrolytic cell. Although hearing aids are one of the most common CMOS circuits presently designed to be powered by a 1.5 volt power supply, a variety of other compact electronic devices may ultimately be reduced to a size where they will be powered by a single miniature battery.
Referring to
FIG. 1A
, a general problem in low voltage circuit design is that of a circuit element
105
(shown in phantom) requiring a shunt switch
110
comprised of one or more MOSFET transistors, such as an n-channel MOSFET transistor
115
and a p-type MOSFET transistor
120
forming a transmission gate shunt switch
110
. An ideal switch has an infinite conductance (zero-resistance) in its on-state and an infinite resistance (zero conductance) in its off state. However, in low voltage circuit design the switch
110
typically has a significant resistance in its on-state. Additionally, in its “off” state, the low voltage switch
110
may also act as a parasitic current/voltage source, altering the voltage at circuit nodes
125
,
130
coupled to the shunt switch. In many low-voltage op-amp circuit applications, the non-ideal characteristics of shunt switch
110
degrades the performance of circuit elements
105
coupled to shunt switch
110
.
It is difficult at a low power supply voltage to operate a MOSFET switch with both a low on-resistance and acceptable turn off-behavior (e.g., low parasitic turn-off charge injection). CMOS switches, when driven with 3.0 V to 5.0 V gate drive signals, may be readily operated in a so-called “ohmic” region in which the transistors of the switches have a low on-resistance. The ohmic region of an n-channel MOSFET is typically defined as occurring at a voltage for which the gate-source voltage, V
GS
, of the MOSFET is greater than the drain-source voltage, V
DS
, plus a threshold voltage, V
TN
, or V
GS
>V
DS
+V
TN
. In the ohmic region, the source-drain current, I
DS
, is proportional to the square of the gate-source voltage minus the threshold voltage, or I
DS
=k(V
GS
−V
TN
)
2
, where k is a constant. For a gate-source voltage above the threshold voltage but below the ohmic region, an n-channel MOSFET operates in a so-called linear or triode region where the drain source voltage increases linearly with drain source voltage, which is expressed mathematically as: I
DS
=2k[(V
GS
−V
TN
) V
DS
−0.5 V
DS
2
]. The on-resistance, R
DS
, is very high in the linear region, and is given by the expression: R
DS
=½k[(V
GS
−V
TN
)−0.5 V
DS
], where k is a constant proportional to the width of the transistor.
A p-channel MOSFET has a similar triode and ohmic behavior but with reference to different voltage polarities. A p-channel MOSFET enters the triode region when the source-gate voltage V
SG
is greater than a (positive) threshold value, V
TP
and the source-drain voltage, V
SD
is less than the source-gate voltage minus the threshold value, which is expressed as: V
SD
<V
SG
−V
TP
. The corresponding p-channel drain current is: I
SD
=2k[(V
SG
−V
TP
) V
SD
−0.5 V
SD
2
] and the corresponding on-resistance is: R
SD
=½k[(V
SG
−V
TP
)−0.5 V
SD
].
FIG. 1B
shows the on-resistance of shunt switch
110
as function of input signal level for a constant supply voltage. The resistance of n-channel MOSFET
115
and p-channel MOSFET
120
is shown along with the parallel resistance of switch
110
as a whole.
FIG. 1B
is for one selection of drain-source voltage. More generally, a family of curves must be drawn for the on-resistance as function of both source-drain voltage and gate-source voltage (PH
1
and PH
2
in FIG.
1
A). For source-drain and gate voltages corresponding to an on-state in the triode region of an individual MOSFET
115
,
120
, the conductance per unit of gate width is low. Consequently, the gate width of each MOSFET transistor may have to be hundreds of microns wide to have a reasonable on-resistance of switch
110
. However, increasing the gate width is not a viable solution in many low voltage circuit designs. One problem is that large area shunt switches
110
increase the size, and hence the cost, of a circuit. Another problem is that increasing the gate width of MOSFET switches
115
,
120
increases the non-ideality of switch
110
in regards to its turn-off behavior.
Parasitic charge injection and capacitive feedthrough are the two main deleterious effects which occur in wide gate width MOSFETs at turn off. Since both parasitic charge injection and capacitive feedthrough increase with gate width, increasing the gate width of a MOSFET switch to reduce its on-resistance results in the tradeoff that parasitic charge injection and capacitive feedthrough increase in the off-state.
Parasitic charge injection is, as its name implies, the undesired injection of charge from a MOSFET as it is turned-off. When MOSFET transistors are turned off, channel charge must flow out from the channel region of the transistor to the drain and source junctions. This causes parasitic charge injection every time the switch
110
is turned off. The total channel charge in a n-channel MOSFET increases with gate width and is typically expressed mathematically as: Q
CH
=WLC
OX
(V
GS
−V
TN
), where Q
CH
, is the channel charge, W is the gate width, L is the gate length, and C
OX
is the oxide capacitance. A similar expression also describes to describe the total charge in an p-channel MOSFET but with different polarity of charge, p-type threshold voltage, and source-g
Coudert Brothers LLP
Le Dinh T.
The Engineering Consortium, Inc.
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