Electric lamp and discharge devices – With gas or vapor – Three or more electrode discharge device
Reexamination Certificate
1999-01-26
2002-01-08
Patel, Vip (Department: 2875)
Electric lamp and discharge devices
With gas or vapor
Three or more electrode discharge device
C313S582000
Reexamination Certificate
active
06337538
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from Japanese Patent Application No. 10-196800 filed Jun. 25, 1998, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a plasma display panel and a method of manufacturing the same and, more particularly, to a composition of a dielectric layer of such a plasma display panel that covers both transparent and bus electrodes thereof.
2. Description of the Related Art
A plasma display panel (“PDP”) is attracting attention in the field of displays as a full-color display apparatus having a large size display area. Particularly, an AC type PDP of a 3-electrode surface discharge model has a structure in which a plurality of display electrode pairs for generating surface discharges are formed on a substrate on the display surface thereof and are then covered with a dielectric layer; address electrodes, orthogonal to the display electrodes, and a phosphor layer covering the address electrodes are formed on the substrate on the rear surface thereof. An image to be displayed is written in the form of wall charges while discharge is sequentially generated between the display electrodes and the address electrodes with one display electrode used as a manipulating electrode. Thereafter, a sustaining voltage is impressed across the display electrode pairs to generate a sustaining discharge. This is the basic operation of known PDP's.
A full-color display can be realized when the phosphor layers of three primary colors are energized by the ultraviolet rays generated by the sustaining discharge and emit the corresponding fluorescent colors of RGB (red, green, blue). Therefore, for the emission of color from the phosphor layer on the substrate on the rear surface side, a transparent electrode material is formed on the substrate on the display electrode pairs. Moreover, a display electrode structure of a transparent electrode with a metal bus electrode formed thereon is generally employed to afford a reduced resistance value of the display electrode.
The transparent electrode material is a semiconductor typically formed of ITO (e.g., a mixture of indium oxide In
2
O
3
and tin oxide SnO
2
). The conductivity of the transparent electrode is low in comparison with that of metal. Therefore, a fine metal conductive layer is added as the metal bus electrode on the transparent electrode to enhance its conductivity.
A dielectric layer covering the transparent electrodes and the bus electrodes is traditionally formed by depositing a low melting point glass paste layer on the substrate and then baking it under a high temperature, for example, 600° C. Such a high temperature baking presents a problem in that the transparent electrode is reduced in thickness or even is lost, i.e., disappears, altogether. This occurs because a battery effect is generated between the transparent and bus electrodes due to the difference in the ionization tendency between the materials of the stacked transparent and bus electrodes. If the transparent electrode becomes thinner or is lost altogether, the sustaining discharge voltage between the display electrodes of each pair rises and, as a result, achieving a stable drive of the PDP becomes difficult. The present inventors have proposed in Japanese Patent Application No. Hei 9-038932 that a rise of the resistance value of the transparent electrode can be controlled by mixing a transparent electrode material with the dielectric material. However, the mixture of the transparent electrode material cannot solve the problem of the loss of the transparent electrode by the battery effect between the transparent electrode and bus electrode, thus leaving unsolved the problem that a local transparent electrode is lost.
The reason why the transparent electrode is lost is not always apparent, but it can be assumed that the oxidation-reduction reaction, based on the battery effect between the transparent electrode and bus electrode, is generated when the dielectric layer is baked under a high temperature, causing the transparent electrode material to dissolve into the dielectric layer.
SUMMARY OF THE INVENTION
Therefore, considering the problem discussed above, it is an object of the present invention to provide a plasma display panel and a method of manufacturing the same which can prevent local disappearance of the transparent electrode.
Moreover, it is another object of the present invention to provide a plasma display panel and a method of manufacturing the same that controls a sustaining discharge voltage to a lower value by reducing a resistance of the transparent electrode.
To attain the objects explained above, the present invention proposes a plasma display panel comprising transparent electrodes, bus electrodes and a dielectric layer covering these electrodes on at least one substrate of a pair of substrates positioned in opposed relationship to each other via a discharge space, wherein a main element of the composition of the bus electrode is included in the composition of the dielectric material.
Moreover, the present invention is also characterized in that the bus electrode is mainly composed of copper oxide, which is also included in the dielectric layer. Local losses of the transparent electrode seem to be prevented, even after undergoing the high temperature process because the main element of the bus electrode is included in the dielectric material.
REFERENCES:
patent: 4109176 (1978-08-01), Ernsthausen et al.
patent: 5793158 (1998-08-01), Wedding, Sr.
patent: 0 788 131 (1997-08-01), None
patent: 5-165042 (1993-06-01), None
patent: 7-282979 (1995-10-01), None
Patent Abstracts of Japan, vol. 098, No. 009, Jul. 31, 1998 and JP 10 112265 A (Matsushita Electric Ind Co Ltd), Apr. 28, 1998.
Patent Abstracts of Japan, vol. 018, No. 623 (E-1635), Nov. 28, 1994 and JP 06 243788 A (Hokuriku Toryo KK), Sep. 2, 1994.
Japanese Laid Open Patent No. 5-165042, of the Patent Abstract of Japan, Jun. 29, 1993.
Japanese Laid Open Patent No. 10-112265, respectively of the Patent Abstract of Japan and “Scope of Patent Claim” in English and Japanese, Apr. 28, 1998.
Awaji Noriyuki
Betsui Keiichi
Tadaki Shinji
Fujitsu Limited
Patel Vip
Staas & Halsey , LLP
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